09-06-2015 11:05 AM
I am trying to save the ports on one of my IPs saved during netlist generation process. The ports are not connected to anything at the moment. The idea is to use Inserter to add chipscope ILAs for these signals and some FSL buses which I cannot chipscope from the EDK directly.
So far in my ucf file I've tried:
NET "<IPCore>/PortName" KEEP
make these ports new connection - so I have a net name
NET "<net_name>" KEEP
and none of them saves the nets from optimization.
Is there something I am missing from keeping these nets from optimzation?
My env: I am using ISE14.7
09-06-2015 11:10 AM
Try using Save Net Flag constraints. Check additional details at page #245 from below UG
09-06-2015 09:55 PM - edited 09-06-2015 09:56 PM
Try using MARK_DEBUG attribute.
Refer to page-163 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf for syntax details.
Also Refer to this article http://www.xilinx.com/support/answers/41246.html
09-06-2015 09:57 PM
Are they getting optimized in synthesis or implementation. Did you try assigning debug net's in the elaborate design and then save the constraints, the tool should write the appropriate constraints for you.
09-07-2015 04:30 AM
09-07-2015 02:56 PM
The attribute mark_debug does not help saving the nets during the optimization phase at this point. The ports are not connected to anything though.
09-07-2015 10:49 PM
If you are trying to probe a signal, then why are you keeping it open? You can directly probe the signal of interest right?
Ideally if you are applying the constraitns correctly the net should be saved from trimming.
09-09-2015 09:44 AM
The main issue is I want to probe these ports along with FSL buses at the same time. However, I cannot probe FSL buses from XPS directly - no chipscope option I found to do so (XPS->DEBUG->DEBUG_OPTIONS->ADD CHIPSCOPE PERIPHERAL -ILA/VIO/AXI-Monitor) so I have to use Core Inserter to probe FSL buses, but the ports I want to probe get optimized out.