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anikitos25
Visitor
Visitor
4,654 Views
Registered: ‎07-08-2014

UCF attribute to keep the ports

Hi all,

 

I am trying to save the ports on one of my IPs saved during netlist generation process. The ports are not connected to anything at the moment. The idea is to use Inserter to add chipscope ILAs for these signals and some FSL buses which I cannot chipscope from the EDK directly.

 

So far in my ucf file I've tried:

 

NET "<IPCore>/PortName" KEEP

or

make these ports new connection - so I have a net name

NET "<net_name>" KEEP

 

and none of them saves the nets from optimization.

 

Is there something I am missing from keeping these nets from optimzation?

 

My env: I am using ISE14.7

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ashishd
Xilinx Employee
Xilinx Employee
4,652 Views
Registered: ‎02-14-2014

Hello @anikitos25,

 

Try using Save Net Flag constraints. Check additional details at page #245 from below UG

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

Regards,
Ashish
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vemulad
Xilinx Employee
Xilinx Employee
4,625 Views
Registered: ‎09-20-2012

Hi @anikitos25

 

Try using MARK_DEBUG attribute. 

 

Refer to page-163 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf for syntax details.

 

Also Refer to this article http://www.xilinx.com/support/answers/41246.html

 

Thanks,

Deepika.

Thanks,
Deepika.
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athandr
Xilinx Employee
Xilinx Employee
4,623 Views
Registered: ‎07-31-2012

Are they getting optimized in synthesis or implementation. Did you try assigning debug net's in the elaborate design and then save the constraints, the tool should write the appropriate constraints for you.

Thanks,
Anirudh

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

The "Preserve unused input" did not work in your design because these inputs were not defined in the netlist compiled in NGDBuild.



This is due to XST optimizing away inputs which have no logic connected to them.



To prevent XST from removing inputs, instantiate IBUFs primitives in your design, and connect the output pin of the IBUFs to a signal marked with a KEEP attribute.



NGDBuild will then give you a warning stating that the output signal of the IBUF has no load, which is correct.
Thanks and Regards
Balkrishan
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anikitos25
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Registered: ‎07-08-2014

The attribute mark_debug does not help saving the nets during the optimization phase at this point. The ports are not connected to anything though. 

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athandr
Xilinx Employee
Xilinx Employee
4,597 Views
Registered: ‎07-31-2012

If you are trying to probe a signal, then why are you keeping it open? You can directly probe the signal of interest right?

Ideally if you are applying the constraitns correctly the net should be saved from trimming.

Thanks,
Anirudh

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anikitos25
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Registered: ‎07-08-2014

The main issue is I want to probe these ports along with FSL buses at the same time. However, I cannot probe FSL buses from XPS directly - no chipscope option I found to do so (XPS->DEBUG->DEBUG_OPTIONS->ADD CHIPSCOPE PERIPHERAL -ILA/VIO/AXI-Monitor) so I have to use Core Inserter to probe FSL buses, but the ports I want to probe get optimized out.

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