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@sgthedreamer95
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Registered: ‎04-11-2016

VHDL Counter of Ones

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Hey guys. 

I need to do something but I dont know exactly how to.

When load = 0, order the array_vector of input. In this case D(8 bits).

This is the problem: I have a binary inputo of 8 bits and I need to put the Zeros to the left and the Ones to the right.

 

 

for example, if D(in) = "01101100", (4 Ones and 4 0s), Q(out) <= "11110000".

Not in a combinational synthesis. Just secuencial.

If you guys have ideas about how to solve it :D I ll be so happy :D..

Have a nice day.

 

Code mine, this part goes there >>>

 

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------- Entity Definition ------------------------------------------------------
entity punto_2 is
port
(
-- Input ports
     reset, clk,load : in std_logic;
     D                       : in std_logic_vector (7 downto 0);
-- Output ports
    Q                       : out std_logic_vector (7 downto 0)
);
end punto_2;
---------------------- Architecture Definition ----------------------------------
architecture rtl of punto_2 is
---------------------- Signals Definition ---------------------------------------

begin
process (reset, clk,load) is
begin
       if reset = '1' then
         Q <= "00000000";
       elsif rising_edge (clk) then
            if (load = '1') then
                 temp <= D;-- This part is mine, It's just a register. 
             elsif (load='0') then --HEREEEEE! the important part.

 


         ------------- HERE GOES THE CODE I NEED
            end if;
       end if;
  end if;
Q<= temp;
end process;
----------------------------------------------------------------------------------------
end rtl;

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1 Solution

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u4223374
Advisor
Advisor
24,347 Views
Registered: ‎04-26-2015

Well, the really easy way is to just have a ROM-based lookup table. 256 8-bit values will easily fit into a 9K block RAM, so you'd just use the input byte as an address and the RAM would output the correct byte.

 

Otherwise, I suggest simply using a shift register to shift the value right (or left) by one element on each clock cycle. If the lowest (or highest, if you shift right) bit is 1 then you shift a 1 into the output register, otherwise you do nothing. In Verilog, because I'm hopeless at VHDL:

 

reg [7:0] regOut;
reg [7:0] temp;

always @(posedge clk) {
	if (reset) begin
		regOut <= 8'b0;
		temp <= 8'b0;
	end else if (load) begin
		regOut <= 8'b0;
		temp <= D;
	end else begin
		temp <= {1'b0,temp[7:1]};
		if (temp[0]) begin
			regOut <= {regOut[6:0],1'b1};
		end
	end
end

You don't even need to detect the end of the byte; that is dealt with automatically.

View solution in original post

8 Replies
@sgthedreamer95
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14,266 Views
Registered: ‎04-11-2016

Sorry for the first part. Its Ones to the left and Zeros to the right :).

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vijayak
Xilinx Employee
Xilinx Employee
14,249 Views
Registered: ‎10-24-2013

Hi @sgthedreamer95

 

Read the input array & compare with 1/0. Then based on the result you can arrange that in the output array.

Thanks,Vijay
--------------------------------------------------------------------------------------------
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@sgthedreamer95
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Registered: ‎04-11-2016
That's a good idea, but i cant's use for loop syntax, there is another way i can do that? read the input and determine the number of zeros or ones? , then its easy.
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vijayak
Xilinx Employee
Xilinx Employee
14,238 Views
Registered: ‎10-24-2013

Hi @sgthedreamer95

If using loop is a limitation, you may try direct indexing (like a(1)...). This may endup in little long code compared to loop logic.

Thanks,Vijay
--------------------------------------------------------------------------------------------
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u4223374
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24,348 Views
Registered: ‎04-26-2015

Well, the really easy way is to just have a ROM-based lookup table. 256 8-bit values will easily fit into a 9K block RAM, so you'd just use the input byte as an address and the RAM would output the correct byte.

 

Otherwise, I suggest simply using a shift register to shift the value right (or left) by one element on each clock cycle. If the lowest (or highest, if you shift right) bit is 1 then you shift a 1 into the output register, otherwise you do nothing. In Verilog, because I'm hopeless at VHDL:

 

reg [7:0] regOut;
reg [7:0] temp;

always @(posedge clk) {
	if (reset) begin
		regOut <= 8'b0;
		temp <= 8'b0;
	end else if (load) begin
		regOut <= 8'b0;
		temp <= D;
	end else begin
		temp <= {1'b0,temp[7:1]};
		if (temp[0]) begin
			regOut <= {regOut[6:0],1'b1};
		end
	end
end

You don't even need to detect the end of the byte; that is dealt with automatically.

View solution in original post

@sgthedreamer95
Visitor
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14,018 Views
Registered: ‎04-11-2016

@

 

if (temp[0]) begin
regOut <= {regOut[6:0],1'b1};

 :D And thats exactly what I need, I just need to understand what that line does. If you could help me with that, i ll really apreciate that man.

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@sgthedreamer95
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Visitor
14,009 Views
Registered: ‎04-11-2016

@u4223374 I dit it!, take me a little but i understand you, THANKS A LOT MAN!!!!!!!!!!! . 

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u4223374
Advisor
Advisor
13,990 Views
Registered: ‎04-26-2015

@sgthedreamer95

 

I think you've figured it out for yourself, but that line just shifts the ouput register to the left by one place, and inserts a 1 at the right end. Obviously reversing it (so you end up with the ones on the left and zeros on the right) would be trivial.

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