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xspai
Visitor
Visitor
3,876 Views
Registered: ‎11-04-2013

[Vivado 12-1433]

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My first post and yes I did search if others got the following error:

CRITICAL WARNING: [Vivado 12-1433] Expecting a non-empty list of cells to be added to the pblock.  Please verify the correctness of the <cells> argument.

 

It comes from the following constraint:

add_cells_to_pblock pblock_pcie0 [get_cells [list *fS2MsgOut*]]

 

When I execute the tcl command "get_cells [list *fS2MsgOut*]", I got garbled output in tcl console. After cutting and pasting the

output, I saw valid text (cells) but rather a very long list.

 

I'm confused why the tool thinks that the list is empty.

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vijayak
Xilinx Employee
Xilinx Employee
6,614 Views
Registered: ‎10-24-2013

Hi @xspai

Please follow the procedure given to draw the pblocks.

http://www.xilinx.com/support/answers/59424.html

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug938-vivado-design-analysis-closure-tutorial.pdf

Thanks,Vijay
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balkris
Xilinx Employee
Xilinx Employee
3,854 Views
Registered: ‎08-01-2008
The same error discussed in this post
https://forums.xilinx.com/t5/Design-Entry/3rd-party-IP-integration-in-Vivado/td-p/538723

check this user guide as well
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug835-vivado-tcl-commands.pdf
Thanks and Regards
Balkrishan
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vijayak
Xilinx Employee
Xilinx Employee
6,615 Views
Registered: ‎10-24-2013

Hi @xspai

Please follow the procedure given to draw the pblocks.

http://www.xilinx.com/support/answers/59424.html

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug938-vivado-design-analysis-closure-tutorial.pdf

Thanks,Vijay
--------------------------------------------------------------------------------------------
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