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swood
Visitor
Visitor
3,386 Views
Registered: ‎09-25-2013

Vivado 13.2 Zynq 7000 Embeded design with Custom block IP Implementation Error

Hi,

 

I am using Vivado 13.2 to implement an embeded deisgn on Zynq 7000. Here is my design flow

 

1) created a new project my_ip, which contains 1 ngc file and 2 Xilinx FIFOs that are generated from Xilinx Fifo Generator.

2) package my_ip, added .ngc file, and the 2 fifo.xci files in the IP File group under syntheis and implementation

3) created the top level project, add zynq7 procession system, add my_ip, auto connect

4) run synthesis. pass

5) run implementation. 2 critial warnings: could not resove non-primitive black box "fifo0"/ "fifo1"

6) Opt design failed: Blackbox "fifo0" cannot be found in the existing library.

 

I have searced related topics regarding this matter and think I have follow the tips of adding the .xci files when packaging IP. Please let me know if I missed any other steps.

 

Thanks!

 

Best,

 

Shinya

 

 

 

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1 Reply
siktap
Scholar
Scholar
3,366 Views
Registered: ‎06-14-2012

Hi Shinya

This issue is commonly seen in an IPI design.

It is caused by either of the following settings in the project being packaged as an IP:

    • Out-Of-Context.
      Ensure that there is no Out-Of-Context IP in the project before you package it.
  • Attributes Box Type in the RTL code.
    Box Type settings will prevent Vivado from synthesizing the module in a packaged IP as the top level design will consider it as a black box.
    As a result implementation will likely fail with a blackbox error or attached logic will be trimmed due to the missing component.

Also, please check if you are following this process.

http://www.xilinx.com/support/answers/60975.html

 

Regards

Sikta

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