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Visitor harple492010
Visitor
1,432 Views
Registered: ‎10-12-2014

chipscope pro core generation and using them in the design

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Hi ,

           I was trying to use Chipscope Pro to debug my FPGA (Spartan 6 : SP605 ) implementation . I wanted to place one ILA and one VIO core at the top module and one ILA and one VIO at the sub level module .

 

Design Hirarchy 

 

TOP ------------------- ( ILA and VIO)

     |  

     |-- A1

     |-- B1

     |-- C1

           |

           |---C2 ----------( ILA and VIO)

 

 

 

(1) Where do I need to instantiate ICON  core ?

(2) How many ICON cores do I need  ?

(3) How "control" signals are connected between ICON core/s and ILA/VIO core/s  ?

 

I would appreciate your help answering these questions .Any documentation/tutorial/apps notes would be appreciated.

 

-Hardik 

 

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Xilinx Employee
Xilinx Employee
1,802 Views
Registered: ‎02-06-2013

Re: chipscope pro core generation and using them in the design

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Hi

 

 

Refer below docs

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/ug750.pdf

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/PlanAhead_Tutorial_Debugging_w_ChipScope.pdf

 

http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/chipscope_pro_sw_cores_ug029.pdf

Regards,

Satish

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Xilinx Employee
Xilinx Employee
1,803 Views
Registered: ‎02-06-2013

Re: chipscope pro core generation and using them in the design

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Hi

 

 

Refer below docs

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/ug750.pdf

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/PlanAhead_Tutorial_Debugging_w_ChipScope.pdf

 

http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_process_analyze_design_using_chipscope.htm

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/chipscope_pro_sw_cores_ug029.pdf

Regards,

Satish

--------------------------------------------------​--------------------------------------------
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