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sunayana.chskradhar
Participant
Participant
4,154 Views
Registered: ‎10-23-2014

data memory access cycles in arm cortex a9 of zynq

Hello All,

I am searching for data memory access cycles in arm cortex a9 which should include arbitration overhead by specific bus (AXI or LMB etc). I searched it in the arm cortex and microblaze manual. Please tell me where i can find it.

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saradapr
Explorer
Explorer
3,998 Views
Registered: ‎10-14-2015

Hi @sunayana.chskradhar,

 

As this is a Zynq any peripheral that is not included as part of the PS is going to be in the PL, which being configurable with an HDL means that the latency of the entire path isn't set in stone.

Arbitration overhead will have to account for the number of things being serviced, which can vary and the arbiter itself add varying amounts of latency depending on the implementation. To determine the latency to a memory on the AXI would require analysis of a worst and best case scenario of the access knowing the arbitration latency and the PS latency for the access.

 

Please refer also 

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug1145-sdk-system-performance.pdf

 

Thanks,

Sarada

 

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