12-06-2015 11:53 PM
Hi, I am trying to implement DES algorithm in spartan 3e starter board. I m using ISE 14.7 and all the modules are written in vhdl. I have included all the files in a project. Is there anyone who would be kind enough to help me on how to create the user constraint files for 64 bit input and key and get at least a simulation result...pls.
12-07-2015 12:40 AM
12-07-2015 10:52 PM
@azizur1727 You mention 64-bit input but in your thread title you refer to only J1, J2 & J4 which can support only 12-bits. Can you help explain what you are trying to do.
If you just are driving inputs to J1, J2, J4 and need help on UCF, below are the steps
1. Determine what is the signalling standard for your interface and set Bank 0 VCCO accordingly using Jumper JP9. Headers J1, J2,J4 are connected to Bank 0
2. Replace LVTTL below with your I/O standard you plan to use along with necessary slew rates and drive strength. You will have to replace the Net names based on the signal names in your code.
12-09-2015 08:23 PM
Thank you so much guys for your quick reply. @gnarahar I am not sure about the title coz I did not even know about J1,J2 and J4 pin. However .....could you please help me with some more step by step instructions on how to give 64 bit input and getting 64 bit output. I have data encryption standard (DES) algorithm codes in only vhdl module...no core files.
Is it possible to implement in spartan 3E? Once I tried to synthesize my code and ended up with pack :2309 and pack:18 error.
Do I need to design a UART first for 64 bit input and output?
I am sorry to say again that I am a newbie here....so pleasss don't get upset with me.