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3,345 Views
Registered: ‎01-14-2015

error clock wrapper in timing analysis

Hello everyone,

I need your help please.

I use acctuellement XSG for the implementation of a system in a DS5203.
When I run Timing Analysis before implementing the following error message appears:

"Clock wrapper output is missing or corrupt solution"

 

 
Anyone know how to solve this problem please ?
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Xilinx Employee
Xilinx Employee
3,257 Views
Registered: ‎07-21-2014

Hi,

 

are you facing followin error message?

Hardware co-simulation compilation failed. Could not find a clock wrapper instance in the design

if yes, which version of ISE are you using? this is a known issue in ISE 13.2 and is fixed in ISE 14.1 and later versions.

 

thanks,

Shreyas

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3,128 Views
Registered: ‎01-14-2015

Hi,

Thank you for your reply.
I am using ISE 14.6. In addition I can not use another version since I have a DS5203 FPGA.

What to do please.
Any idea?

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Xilinx Employee
Xilinx Employee
3,121 Views
Registered: ‎01-03-2008

You are not using a DS5203 FPGA as this does not exist, but I do think that you are using a DS5203 board from dSPACE that has a Virtex-5 FPGA on it.

 

Please post the entire error message that was reported by the tools.

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2,647 Views
Registered: ‎01-14-2015

Hi,

 

Thank you for your replay,

 

Error message is:

 

An error occurred in the build of the Xilinx System Generator. Clock wrapper output is missing or corrupt:
E:\test_perso\ADC_Gestion_xilinx_simulation _RTI\timing\ADC_cw.vhd

 

??

 

 

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Newbie
Newbie
1,313 Views
Registered: ‎10-21-2015

Hi! I am facing the same problem! But it seems I've got a sollution: in simulink try to give another name to your FPGA subsystem. Use some very simple name. DON'T USE HYPHENATION SYMBOLS (except of underscore) - ONLY LETTERS. After renaming the FPGA Subsystem go to the Processor Setup Block in the main model and choose the new renamed FPGA subsystem from the list. Restart the Matlab and try again.

Maybe this sollution helps you too.

Good luck,

Alex.

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