cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
4,757 Views
Registered: ‎06-07-2012

errors in synthesis

hi,

greethings.

i had written a code in verilog but errors occured in synthesis(ISE 12.2)

code is....

 

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    10:14:58 06/05/2012
// Design Name:
// Module Name:    lowwpassdb4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lowpassdb4(ww,clk,rst,pipe1,pipe2,pipe33,pipe4);
input signed [81:7]ww;
input clk,rst;
output  signed [18:0]pipe1;
output  signed [18:0]pipe2;
output signed [15:0]pipe33;
output  signed [20:0]pipe4;

reg  signed [18:0]pipe1;
reg  signed [18:0]pipe2;
reg  signed [15:0]pipe33;
reg  signed [20:0]pipe4;
 wire   [1:0]x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14;

assign ww[81:72]=1'b0;
//assign ww[81]=1'b0;
//assign ww[80]=1'b0;
//assign ww[79]=1'b0;
//assign ww[78]=1'b0;
//assign ww[77]=1'b0;
//assign ww[76]=1'b0;
//assign ww[75]=1'b0;
//assign ww[74]=1'b0;
//assign ww[73]=1'b0;
//assign ww[72]=1'b0;
//
//
assign ww[71]=1'b1;
assign ww[70]=1'b1;
assign  x1={ww[70],ww[71]};

assign ww[69]=1'b1;
assign ww[68]=1'b1;
assign x2={ww[69],ww[68]};

assign ww[67]=1'b1;
assign ww[66]=1'b1;

assign x3={ww[67],ww[66]};

assign ww[65]=1'b1;
assign ww[64]=1'b1;
assign x4={ww[65],ww[64]};

assign ww[63:58]=1'b0;
//assign ww[63]=1'b0;
//assign ww[62]=1'b0;
//assign ww[61]=1'b0;
//assign ww[60]=1'b0;
//assign ww[59]=1'b0;
//assign ww[58]=1'b0;

 


assign ww[57]=1'b1;
assign ww[56]=1'b1;
assign  x5={ww[56],ww[57]};

assign ww[55]=1'b1;
assign ww[54]=1'b1;
assign x6={ww[54],ww[55]};

assign ww[53]=1'b1;
assign ww[52]=1'b1;
assign x7={ww[52],ww[53]};

assign ww[51]=1'b1;
assign ww[50]=1'b1;
assign x8={ww[50],ww[51]};

 

assign ww[49:26]=1'b0;
//assign ww[49]=1'b0;
//assign ww[48]=1'b0;
//assign  ww[47]=1'b0;
//assign  ww[46]=1'b0;
// assign  ww[45]=1'b0;
//assign  ww[44]=1'b0;
//assign  ww[43]=1'b0;
//assign  ww[42]=1'b0;
//assign  ww[41]=1'b0;
//assign  ww[40]=1'b0;
//assign  ww[39]=1'b0;
//assign  ww[38]=1'b0;
//assign  ww[37]=1'b0;
//assign ww[36]=1'b0;
//assign  ww[35]=1'b0;
//assign  ww[34]=1'b0;
//assign  ww[33]=1'b0;
//assign  ww[32]=1'b0;
//assign  ww[31]=1'b0;
//assign ww[30]=1'b0;
//assign  ww[29]=1'b0;
//assign  ww[28]=1'b0;
//
////assign  ww[27]=1'b0;
////assign  ww[26]=1'b0;
//
//
//
assign  ww[27]=1'b1;
assign  ww[26]=1'b1;
assign x9={ww[27],ww[26]};


assign  ww[25]=1'b1;
assign  ww[24]=1'b1;
assign x10={ww[25],ww[24]};


assign ww[23:17]=1'b0;
//assign ww[23]=1'b0;
//assign ww[22]=1'b0;
//assign ww[21]=1'b0;
//assign ww[20]=1'b0;
//assign ww[19]=1'b0;
//assign ww[18]=1'b0;
//assign ww[17]=1'b0;
//

assign  ww[16]=1'b1;
assign  ww[15]=1'b1;
assign x11={ww[16],ww[15]};


assign  ww[14]=1'b1;
assign  ww[13]=1'b1;
assign x12={ww[14],ww[13]};

assign  ww[12]=1'b1;
assign  ww[11]=1'b1;
assign x13={ww[12],ww[11]};


assign  ww[10]=1'b1;
assign  ww[9]=1'b1;

assign x14={ww[10],ww[9]};


assign ww[8]=1'b0;

assign ww[7]=1'b0;

always@(posedge clk or posedge rst)
begin
    if(rst==1'b1)
       begin

   pipe1[18:0]<=19'b0;
   pipe2[18:0]<=19'b0;
     pipe33[15:0]<=16'b0;
   pipe4[20:0]<=20'b0;

        end
 else
  begin
    pipe1[18:0]<={ww[81:72],x1,x2,x3,x4,ww[63]};
   pipe2[18:0]<= {ww[62:58],x5,x6,x7,x8,ww[49:44]};
   pipe33[15:0]<= ww[43:28];
   pipe4[20:0]<={x9,x10,ww[23:17],x11,x12,x13,x14,ww[8:7]};
  end
end
endmodule

 

 

errors are:

ERROR:HDLCompiler:1401 - "\External lab HDL\pipe\../../raji/pipeline.v" Line 94: Signal ww[71] in unit lowpassdb4 is connected to following multiple drivers:
ERROR:HDLCompiler:1379 - "\External lab HDL\pipe\../../raji/pipeline.v" Line 48: Driver 0: output signal of instance Power
ERROR:HDLCompiler:1379 - "\External lab HDL\pipe\../../raji/pipeline.v" Line 94: Driver 1: output signal of instance Ground

 

 

please help me

0 Kudos
2 Replies
Highlighted
Teacher
Teacher
4,756 Views
Registered: ‎09-09-2010

Re: errors in synthesis

Maybe you have the same underlying problem as in this thread:
http://www.fpgarelated.com/usenet/fpga/show/106147-1.php

Check warnings for signal optimization messages.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Highlighted
Professor
Professor
4,755 Views
Registered: ‎08-14-2007

Re: errors in synthesis

Maybe XST is complaining that you are assigning a value to an input?

 

input signed [81:7]ww;

 

assign ww[71]=1'b1;

 

This would have a multiple driver error because the signal is already driven

by the port.

 

The other error messages are probably nonsense that occurs when you have power or ground

signals as one of the offending drivers.

 

By the way, each of your error messages is incomplete.  If you copied these from the

"Errors" tab in the ISE GUI, you should be aware that this tab only shows the first line

of each error, and you need to go the the appropriate report file to see the rest of the

error.  In the case of:

 

ERROR:HDLCompiler:1401 - "\External lab HDL\pipe\../../raji/pipeline.v" Line 94: Signal ww[71] in unit lowpassdb4 is connected to following multiple drivers:

 

You should have had more clues as to the places where the signal ww[71] was being driven.

 

 

-- Gabor

-- Gabor
0 Kudos