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houssem1992
Observer
Observer
4,271 Views
Registered: ‎06-28-2015

fir compiler vhdl code

Hi All ,

 

i want to create a custom fir-filter but i don t have enough knowledge to design it . so can i access to the fir compiler vhdl-code of vivado , which can help me to understand the the Stream Interface and the method  to do custom  IP blocks .

 

I have the vhdl of a simple fir filter and i want to implement it  on zedboard .  i know that i need a Stream Slave and a Stream Master for the block but i don t know how can  i insert the vhdl code  into the architecture of Zynq .  please help me .

signal a,b,c :std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0):=(others => '0');
                signal y :std_logic_vector(34 downto 0 ):= (others => '0');
                signal k1:std_logic_vector(2 downto 0):="011";
                signal k2:std_logic_vector(2 downto 0):="010";
            -- Add user logic here
    begin
    -- User logic ends
                                                                    
    
        -- Add user logic here
      
          process(X,M_AXIS_ACLK) 
          
          begin
          if (M_AXIS_ACLK='1') and (M_AXIS_ACLK'event) 
          then
                  -- Verzögerung von Inputsignale bei jedem clockTakt 
                      c<=b;
                      b<=a;
                      a<=X;
                      y<=(k1*a + k2*c);  -- Ausgangs Signal 
                      M_AXIS_TDATA<=y(31 downto 0 ); -- Ausgangs auf die 32 Bits begrenzen 
          
                      
           end if ;           
                      
          
          end process ;

thanks

houssem

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3 Replies
balkris
Xilinx Employee
Xilinx Employee
4,269 Views
Registered: ‎08-01-2008

you can do it with custom peripheral option
http://zedboard.org/content/creating-custom-peripheral

http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html

http://japan.xilinx.com/direct/ise7_tutorials/import_peripheral_tutorial.pdf
Thanks and Regards
Balkrishan
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syedz
Moderator
Moderator
4,267 Views
Registered: ‎01-16-2013

Hello @houssem1992,

 

Why dont you use the FIR compilier LogicCORE IP which will be present in IP catlog of Vivado.

Check the product IP guide:

http://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf

 

Once you generate the IP, Vivado will create its instantiation template which can direcly be use to instantiate this IP in any Vivado design.

 

Capture.PNG

 

 

--Syed

 

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houssem1992
Observer
Observer
4,157 Views
Registered: ‎06-28-2015

i musst do the block without the Fir compiler and i want to test my IP block in SDK because after this step i will implement an adaptive filter. so it will be greatly helpful , if someone help me to write the code of a simple fir filter in vivado with vhdl or verilog .

the block of a Slave Stream for Input and Master Stream for output . I write a code , but i have always problems when i test it in SDK .

 

this is process which i want to implement it on Zedboard.

 

  process(X,M_AXIS_ACLK) 
          
          begin
          if (M_AXIS_ACLK='1') and (M_AXIS_ACLK'event) 
          then

                      c<=b;
                      b<=a;
                      a<=X;
                      y<=(k1*a + k2*c);  -- Ausgangs Signal 
                      M_AXIS_TDATA<=y(31 downto 0 );  
          
                      
           end if ;           
                      
          
          end process ;

thanks

houssem

 

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