I have instantiated the floating point IP for addition, then I run the simulation. but the output are fixed to zero value even after forcing the inputs .
here is my VHDL code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity test_add is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
aa,bb : in STD_LOGIC_VECTOR (31 downto 0);
cc : out STD_LOGIC_VECTOR (31 downto 0));
end test_add;
architecture Behavioral of test_add is
COMPONENT FPU_add_2inputs
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal cc_valid : std_logic ;
signal ccc : STD_LOGIC_VECTOR (31 downto 0);
begin
ADD : FPU_add_2inputs
PORT map (
aclk => clk,
s_axis_a_tvalid => '1',
s_axis_a_tdata => aa,
s_axis_b_tvalid => '1',
s_axis_b_tdata => bb,
m_axis_result_tvalid => cc_valid,
m_axis_result_tdata => ccc
);
cc <= ccc;
end Behavioral;
Hello,
Even when I try to test the IP as block design and simulate the wrapper it have the same behaviour: output are inchangeable and set to zero value. 5 I use VIVADO 2016.2).
Pleasz help me.
Regards
