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Adventurer
Adventurer
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Registered: ‎03-31-2014

how to write to DDR in Zynq from PL

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Anonymous
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So the HP port follows the AXI protocol, so there are no special commands or procedures from the masters point of view. You just use the DDR physical address. The RAM in Zynq starts at address 0 but theres a small gotcha - watch out for OCM sections which may overlay the lowest 256K of the RAM address space. There is a register in the SLCR peripheral that can get this right for you (moving those sections out of the way in the address map).

 

Stepping back a little, ultimately, with Zynq you always need a little bit of software to at least get setup even if software is not in your primary run-time datapath. The PS DDRC, PS/PL interfaces and maybe the HP ports need to be configured on boot independently of any traffic and before you can send any traffic. You dont need to write any new code, but the Viado generated ps7_init files need to be linked to some software which runs on boot, either FSBL (available via SDK) or U-boot SPL (open source).

 

But while developing, use the ps7_init.tcl script over XMD and run ps7_init and ps7_post_config commands to setup the PS the same way boot software would (NOTE: your project should have DDR and HP port enabled). After that, you should be able to generate working traffing from your master just over standard AXI.

 

Then later you can add your small bit of firmware to your production boot media (whatever media will hold your bitstream).

 

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Anonymous
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Hi,

 

You need to create an IP with an AXI master attachment. You then attach that master to one of the PS AXI slave ports.

- Use the ACP Slave if you need your master to be cache coherent with the ARM processor.

- Use one of the HP ports if you want to do high performance bulk access to only the DDR

- Use the GP slave if your master will talk to other slaves in the PS (like the IO peripherals).

 

Your software (usually FSBL or U-boot) in the PS will need to init the DDR before it will work. If you dont have software yet, this alternatively can be done over the JTAG using the ps7_init.tcl scripts which vivado can generate for you.

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Contributor
Contributor
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Registered: ‎12-30-2015

Hi,

 

If you want to access DDR in baremetal then its simple strainght forward. Use a axi DMA connect your custom Ip to DMA that will send data to DDR. Connect DMA to HP port of PS and that,s all in hardware and simply write application in SDK for that.

 

But if you want to use access DDR in linux then you need to have driver for you ip and also for axi DMA. Otherwise you can use some other way to map memory.

 

Regards

 

Abbas

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Adventurer
Adventurer
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Registered: ‎03-31-2014

@Anonymous

 

Thanks for your response.

 

let a custom AXI master drive one of the HP slave ports of PS to get connected to the DDR controller inside PS.

 

Please clarify , how should the custom  AXI master drive the slave inorder to achieve DDR write and read ? Is there any procedure / set of commands for that?

 

Any reference would be helpful

 

Thanks.

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Adventurer
Adventurer
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Registered: ‎03-31-2014

@abbascit

 

Thanks for your response.

 

I need to do write & read by the PL, and PS not be used. I can't use an application in SDK.

THanks.

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Anonymous
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So the HP port follows the AXI protocol, so there are no special commands or procedures from the masters point of view. You just use the DDR physical address. The RAM in Zynq starts at address 0 but theres a small gotcha - watch out for OCM sections which may overlay the lowest 256K of the RAM address space. There is a register in the SLCR peripheral that can get this right for you (moving those sections out of the way in the address map).

 

Stepping back a little, ultimately, with Zynq you always need a little bit of software to at least get setup even if software is not in your primary run-time datapath. The PS DDRC, PS/PL interfaces and maybe the HP ports need to be configured on boot independently of any traffic and before you can send any traffic. You dont need to write any new code, but the Viado generated ps7_init files need to be linked to some software which runs on boot, either FSBL (available via SDK) or U-boot SPL (open source).

 

But while developing, use the ps7_init.tcl script over XMD and run ps7_init and ps7_post_config commands to setup the PS the same way boot software would (NOTE: your project should have DDR and HP port enabled). After that, you should be able to generate working traffing from your master just over standard AXI.

 

Then later you can add your small bit of firmware to your production boot media (whatever media will hold your bitstream).

 

View solution in original post

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Adventurer
Adventurer
11,275 Views
Registered: ‎03-31-2014

@Anonymous

 

Thanks for an elaborate write-up.

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Visitor
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Registered: ‎02-28-2016

@pete_128

Hi, I'm a green hand of AXI, and I want to creat a custom IP to write and read DDR via PL(ZC702).

Could you send me a simple project about it? My E-mail is wxw_happy@sina.com. Thank you!

 

Weller

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Xilinx Employee
Xilinx Employee
11,182 Views
Registered: ‎02-06-2013

Hi

 

You can use MIG in PL and do transactions to the DDR.

 

Check below doc and the example design created with this core gives you a good starting point.

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_3/ug586_7Series_MIS.pdf

 

Regards,

Satish

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Anonymous
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Hi,

 

You question is slightly ambiguous, are you trying to write to a separate DDR interface implemented in PL (which means you use MIG) or are you trying to just use the existing DDR interface that is part of the PL?

In the latter you just need to follow instructions earlier in thread. For the former, you need the MIG, but this would mean you probably have your own custom board, as the Zynq boards that I know of have their DDR soldered only to the PS DDR.

 

For AXI beginners, you should avoid thinking in terms of Memory, instead just think of it as a generic bus master. The read and write sides are independent, the read side is simpler from a control flow point of view so I would start there. Populate memory using the debugger then see your peripheral reading the data. BFM simulations are a good idea.

 

The governing principle of AXI, is that one on the of the channels  (AR, AW, R, W, B) a transaction occurs on the clock edge if VALID and READY are both set. The slave controls one, the master the other (which way depends on the channel. So any of the 5 channels can back-pressure from either side. For Reads, you only care about AR and R.

 

To perform your first read, hardwire the RREADY signal to '1' and have a state machine set ARVALID to '1' with the ARADDR containing the memory address. You need to deassert ARVALID, after the clock edge when ARREADY goes high (this means the slave accepted your request), otherwise if you leave it up, you are asking for a second read. Then wait until RVALID = '1', and on the clock edge RDATA will be your data. I believe both RVALID and ARREADY could happen at the same time so make the circuits handling the de-assertion and read, independent (looking at some code of mine that is what I have done).

 

The AXI spec ARM IHI 0022D is the documentation.

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