UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
12,216 Views
Registered: ‎03-11-2014

ila debug core clock problem

Jump to solution

Hi everyone,

 

I run into a problem with ila debug core.

I design for a Zedboard and I am using Vivado 2013.3 and I try to capture some signals coming out of a custom IP I designed.

The clock (clk_out1) of this IP is 10 Mhz, coming from a clocking wizard.

The input clock (sys_clk) of the wizard is the 100 Mhz system clock of the board (pin Y9).

 I set up the debug core with clk_out1 as the clock domain of the signals.

When I try to capture the signals, by pressing "run trigger" in the hardware manager nothing happens.

 

If I set the 100 Mhz sys_clk as the clock domain for the signals, the capture is working but of course it is oversampling.

 

Why the debug core is not working with the clock coming out of the clocking wizard, but only with the system clock (going in the clocking wizard)?

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
17,757 Views
Registered: ‎09-20-2012

Re: ila debug core clock problem

Jump to solution

Hi,

 

The JTAG cable’s TCK clock frequency has to be lower than the ILA’s “clk” input frequency.

 

Which cable are you using? If the default cable frequency is greater than 10Mhz(ILA clock frequency), try setting it to a lower value. 

 

cc.jpg

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
10 Replies
Xilinx Employee
Xilinx Employee
17,758 Views
Registered: ‎09-20-2012

Re: ila debug core clock problem

Jump to solution

Hi,

 

The JTAG cable’s TCK clock frequency has to be lower than the ILA’s “clk” input frequency.

 

Which cable are you using? If the default cable frequency is greater than 10Mhz(ILA clock frequency), try setting it to a lower value. 

 

cc.jpg

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Contributor
Contributor
12,200 Views
Registered: ‎03-11-2014

Re: ila debug core clock problem

Jump to solution

This solved the problem.

 

Thanks,

Nikos

0 Kudos
Visitor yinfuyou
Visitor
10,931 Views
Registered: ‎09-02-2014

Re: ila debug core clock problem

Jump to solution

can you tell me , how to use ila,  give me a example,thanks.

0 Kudos
Visitor yinfuyou
Visitor
10,928 Views
Registered: ‎09-02-2014

Re: ila debug core clock problem

Jump to solution

my email:  yinfuyou198947@sina.com 

                                     thanks.

0 Kudos
Xilinx Employee
Xilinx Employee
10,926 Views
Registered: ‎04-16-2012

Re: ila debug core clock problem

Jump to solution

Hi,

 

Here is a nice tutorial: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug936-vivado-tutorial-programming-debugging.pdf

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.
0 Kudos
Xilinx Employee
Xilinx Employee
10,917 Views
Registered: ‎02-14-2014

Re: ila debug core clock problem

Jump to solution
Hello,

First go through chapter #4 from below UG to get the overview of ILA and then do the above mentioned tutorial
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug908-vivado-programming-debugging.pdf
Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Visitor twellington
Visitor
8,135 Views
Registered: ‎03-23-2015

Re: ila debug core clock problem

Jump to solution

Accept as solution - thanks 

 

Yup, this one just bit me in the behind as well, yup also wasted a lot of time like the others -

 

Having ported a working design from old Kintex to new Zynq target, I didn't notice that though old Zylinx box was 5MHz, the new Diligent (I just discovered) was defaulting to 15MHz ... setting back to 5MHz got the ILA working again. 

 

Now I just have to rant to Xilinx a little as Vivado (2015.1) has cause me a lot of wasted time over the last month, in many ways:

 

Why cant the tools help us out a little here, and not just stare back at us with that now familiar blank expression! 

 

And at a more fundamental level, why is the ILS so intimately tied to the JTAG frequency? is it to save on memory or other resources? I have resources to burn in this test project! I remember in a Quartus project (2011 version that is!) completly starting & stopping my SignalTap sample clock with impunity via my own logic to skip non-required states, and mux in different clock divider rates for more/less detail in specific states - all of this to conserve precious trace buffer on a small target (and it made it easier to navigate around the resulting scope) - and it worked flawlessly! Never had to even think about the minimum clock frequencies.

 

 

 

0 Kudos
Voyager
Voyager
5,092 Views
Registered: ‎10-12-2016

Re: ila debug core clock problem

Jump to solution

Really works. Solution Accepted. Thank you Forum people. Thanks Deepika

-Sampath
0 Kudos
4,446 Views
Registered: ‎08-10-2017

Re: ila debug core clock problem

Jump to solution

Thanks deepika.

0 Kudos
Adventurer
Adventurer
1,674 Views
Registered: ‎08-10-2017

Re: ila debug core clock problem

Jump to solution

@vemulad

 

Thank you Deepika. It worked.

0 Kudos