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7,500 Views
Registered: ‎03-09-2016

need example design files for Kintex KC705 and Vivado HLS

I have the Kintex 7 - KC705 board. It will be very helpful if somebody can recommend few example designs to get started with Vivado HLS 2015.4; I tried to find one at the link: http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html#documentation but couldn't end up getting one which runs using HLS (all are for standard Vivado Suite using verilog/VHDL). Also, the ones (example files for Vivado HLS) which come default with Vivado Suite 2015 installations have some problems with the targetted device, generating errors. Any insights on this will be highly appreciable. Thanks in advance.

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4 Replies
Xilinx Employee
Xilinx Employee
7,464 Views
Registered: ‎04-16-2012

Re: need example design files for Kintex KC705 and Vivado HLS

Hello @sourav.chatterjee

 

I dont think there is an example design that targets KC705 and uses both Vivado HLS and Vivado.

 

Thanks,

Vinay

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7,443 Views
Registered: ‎03-09-2016

Re: need example design files for Kintex KC705 and Vivado HLS

Hello @vuppala,

 

Thanks a lot for attending to my query. My subsequent question is: if there is any example design for testing only Vivado HLS with KC705 (the same may not work for Vivado general suite)? If not, is there any other way to test the working Vivado HLS for a beginner having KC705 board? 

 

Looking forward to your reply.

 

Cheers,

Sourav

 

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Xilinx Employee
Xilinx Employee
7,312 Views
Registered: ‎07-23-2012

Re: need example design files for Kintex KC705 and Vivado HLS

Please refer to http://www.xilinx.com/support/answers/66421.html
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6,968 Views
Registered: ‎03-09-2016

Re: need example design files for Kintex KC705 and Vivado HLS

Hello @smarell,

 

thanks a lot for the response and updating me on the hls adaptive filter codes. However when compiled and synthesized it is giving errors on my machine.

 

I have a very specific question. This may seem trivial but I am a beginner with FPGAs and so stuck at this point for a long time. Given the matrix multiplication project (https://drive.google.com/file/d/0B9npOEcoE5duYWpxNmQ0LVhIOW8/view) which comes along with the HLS example design files in Vivado 2015.4 suite and the KC705 Evaluation board; after generating the RTL using the HLS suite, how do I implement and test the output on my FPGA board? Till exporting of the RTL file from HLS I have no problems.

 

More particularly when I use the RTL file from HLS on Vivado Suite to generate bit stream it gives rise to errors. Although I had exported the RTL considering the part number for my board. (Log file is attached)

 

If one could guide me with the required steps for once through the execution and running of one of design files like matrix multiplication on KC705 board it would be really helpful. 

 

Thanks in advance,

Sourav

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