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Adventurer
Adventurer
8,136 Views
Registered: ‎02-22-2016

set up debug clock problem

Hi all,

I'm new in Vivado so I have a problem with a very basic application too.

I have tried to run a 2-input-and in my ac701 board but after the implemantation I have a problem with set up debugging command. I don't  need and use a clock in my program but it asks me a clock during debugging command. I have added the snapshot of the problem.

Why it gives me an error like that and how can I fix it?

Thank you advence

herdinc 

sample.png
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8 Replies
Moderator
Moderator
8,122 Views
Registered: ‎07-01-2015

Re: set up debug clock problem

Hi @herdinc,

 

There are no clocks in the design. That's why tool you are getting undefined clock domain. ILA needs a free running clock to work.

 

Please modify your code by adding clock.

 

entity main is

port(a,b,clk : in std_logic; c: out std_logic);

end main;

 

architecture behavioral of main is 

begin

process(clk)

begin

if(rising_edge(clk)) then

c<=b and a;

end if;

end process;

end behavioral;

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
8,112 Views
Registered: ‎02-22-2016

Re: set up debug clock problem

Hi @arpansur

I have updated my code but this doen't solve my problem. I still get the same error. In my constraint file, I have also added 

create_clock -name sys_clk -period 10 [get_ports clk] command 

 

When I want to add select clock domain to my debug window, in the tcl command window I get error like  

WARNING: [Vivado 12-1023] No nets matched for command 'get_nets -hierarchical -filter {TYPE == "GLOBAL_CLOCK"}'.
WARNING: [Coretcl 2-1122] No objects found.

Thank you,

herdinc

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Moderator
Moderator
8,094 Views
Registered: ‎07-01-2015

Re: set up debug clock problem

Hi @herdinc,

 

Have you ran synthesis again and then set up debug?

 

It should be taken up automatically.

 

Thanks,
Arpan

Thanks,
Arpan
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Adventurer
Adventurer
8,091 Views
Registered: ‎02-22-2016

Re: set up debug clock problem

Hi @arpansur

Thank you very much, I didn't get the ILA file one of chosen mistake while I am sythetizing. Then I have generated the bitstream but there some mistakes. I have observed your constraint file, it is interesting to me that there are some commands associated with ILA. Did you write these commands by yourself or did they generate automaticaly

 

create_clock -period 10.000 -name sys_clk [get_ports clk]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk_IBUF_BUFG]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list a_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list b_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list c_OBUF]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_IBUF_BUFG]

 

 

 

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Adventurer
Adventurer
8,090 Views
Registered: ‎02-22-2016

Re: set up debug clock problem

This is my constraint file, which is written by me

 

set_property PACKAGE_PIN R26 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports c]

set_property PACKAGE_PIN R6 [get_ports a]
set_property IOSTANDARD SSTL15 [get_ports a]
set_property PACKAGE_PIN R7 [get_ports b]
set_property IOSTANDARD SSTL15 [get_ports b]

create_clock -name sys_clk -period 10 [get_ports clk]

 

 

And  I get this message

 

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk.

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Moderator
Moderator
8,077 Views
Registered: ‎07-01-2015

Re: set up debug clock problem

Hi @herdinc,

 

Please assign package pin to clk also. Error message is about single port here it's clk port.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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Adventurer
Adventurer
7,957 Views
Registered: ‎02-22-2016

Re: set up debug clock problem

Hi @arpansur

I have added package pin clk to my .xdc file but it gives me an error 

now my xdc file is updated as

----------

set_property PACKAGE_PIN R26 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports c]
set_property PACKAGE_PIN R6 [get_ports a]
set_property IOSTANDARD SSTL15 [get_ports a]
set_property PACKAGE_PIN R7 [get_ports b]
set_property IOSTANDARD SSTL15 [get_ports b]
create_clock -period 10.000 -name sys_clk [get_ports clk]
set_property PACKAGE_PIN P16 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]

 

set_property MARK_DEBUG true [get_nets a_IBUF]
set_property MARK_DEBUG true [get_nets b_IBUF]
set_property MARK_DEBUG true [get_nets clk_IBUF]
set_property MARK_DEBUG true [get_nets c_i_1_n_0]
set_property MARK_DEBUG true [get_nets clk_IBUF_BUFG]
set_property MARK_DEBUG true [get_nets c_OBUF]
create_debug_core u_ila_0_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0_0]
set_property port_width 1 [get_debug_ports u_ila_0_0/clk]
connect_debug_port u_ila_0_0/clk [get_nets [list clk_IBUF_BUFG]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0_0/probe0]
set_property port_width 1 [get_debug_ports u_ila_0_0/probe0]
connect_debug_port u_ila_0_0/probe0 [get_nets [list a_IBUF]]
create_debug_port u_ila_0_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0_0/probe1]
connect_debug_port u_ila_0_0/probe1 [get_nets [list b_IBUF]]
create_debug_port u_ila_0_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0_0/probe2]
connect_debug_port u_ila_0_0/probe2 [get_nets [list c_i_1_n_0]]
create_debug_port u_ila_0_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0_0/probe3]
connect_debug_port u_ila_0_0/probe3 [get_nets [list c_OBUF]]
create_debug_port u_ila_0_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0_0/probe4]
connect_debug_port u_ila_0_0/probe4 [get_nets [list clk_IBUF]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_IBUF_BUFG]

------------

 

Bu I still get error messages as

 

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] >

clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y143
and clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7

 

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

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Adventurer
Adventurer
7,950 Views
Registered: ‎02-22-2016

Re: set up debug clock problem

Also when I use the other clock pins as an input then I get a message as these are differential closck. I have only find this as an single end clock

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