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pockethercules
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Registered: ‎08-19-2016

strange Xilinx Vivado synthesis behavior with SystemVerilog interfaces

I ran into a strange issue with SystemVerilog interfaces in Vivado synthesis that doesn't make any sense to me. After experimenting a bunch, it almost appears as if Vivado synthesis is not handling my array of interfaces correctly. I created a simple testcase that demonstrates the strange behavior. I have attached an RTL file and a Vivado project file that can be used to duplicate the issue. Just load the xpr and run synthesis.

 

After running synthesis, Vivado reports a ton of critical warnings of type [Synth 8-3352], which report that "multi-driven net <something>[0] with <1st,2nd,3rd,...> driver pin '*'". I can see the multiply driven outputs in the output schematic as well.

 

Whats really strange to me is that I do not see the same issue if I use the commented out lines in my code to handle the translation between interfaces rather than the interface tasks/functions I used in the example.

 

Am I doing something in an unsupported manner?

 

 

-pocket

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balkris
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Registered: ‎08-01-2008

check this ARs
http://www.xilinx.com/support/answers/64364.html

https://forums.xilinx.com/t5/Synthesis/critical-warning-quot-multi-driven-net-quot/td-p/652807
Thanks and Regards
Balkrishan
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pockethercules
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Registered: ‎08-19-2016

balkris -

 

Thanks for the reply. Unfortunately, neither link helps. Prior to posting, I went through the debug steps in AR 64364. This just helped me see exactly what the message says. I am trying to identify why this is happening, not what is happening. I don't believe that the synthesis tool is handling what I coded correctly...

 

-pocket


@balkris wrote:
check this ARs
http://www.xilinx.com/support/answers/64364.html

https://forums.xilinx.com/t5/Synthesis/critical-warning-quot-multi-driven-net-quot/td-p/652807

 

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markcurry
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Registered: ‎09-16-2009

Pocket,

 

I see nothing wrong with your example - it should work.

 

We use Arrays of SystemVerilog interfaces in our code, and it does work ok with Vivado.

Note, that I strongly suggest using at LEAST Vivado 2016.1 ( I know there were some troubles before this version).

 

I've also noted that Vivado seems to have trouble with interfaces that drive interfaces IO signals from within the interface itself - as you're doing in your "unpack()" example.  We don't use them this way, so I've never gotten a concrete feeling for what's causing Vivado trouble.  Your examples seems to be an excellent testcase for Xilinx - they should take this and find out what's causing the trouble.

 

But, if you're just sampling interface signals (from within the interface - or from an imported interface function - like your "pack()" function).  Vivado seems to work fine - from single index to arrays of interfaces.

 

Note also that Vivado still chunks out a lot of invalid warnings around interfaces. It operates properly, but spits out warning messages that are flat out wrong. 

 

Good luck,

 

Mark

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pockethercules
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Registered: ‎08-19-2016

Hi Mark,

 

Thanks for your reply. I ran with 2016.2, so I should be good on the version front. The driver comment concerns me - good to know, but concerning. If I understand what you are saying, that means Xilinx has reduced interface functionality a struct that understands direction.

 

-Pocket

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