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Visitor
Visitor
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Registered: ‎12-12-2014

switching 2 clocks in the same process

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Hi everyone,

I am involved in a project in which I need to switch between 2 clocks to acces one memory. So I have a switch signal to change the clk when I need. Here is the problem, it doesnt switch correctly. I have done dozens of changes (for example trying with only one clock), but with the same result. In the simulation works correctly, but it doesnt in my fpga (spartan 6 LX9).

It starts at state 1 (clk1, switch='0'). Then it changes from state 1 to state 2 (clk2, switch='1') and finally switches again to the state1. Then the states never switch again.

The problem is in the change from the state 2 to state 1. For example, if it starts in the state2 (switch='1') it never goes back to the state2.

 

You can see here the code:

 

 

echo: process(clk1,clk2)
begin
        if (rising_edge(clk1)) and (switch='1') then     --State1
            
            if (cont1 = 500) then   --cont1: counter of the state1
                 switch<='0';
                 FULL<='1';
                 cont1<=0;    
            elsif(cont1 /= 500) then
                 cont1<=cont1+1;

            end if;
          end if;
   
        if rising_edge(clk2) and (switch='0') then --State2
            if (cont = 500) then  --cont: counter of the state2
            switch<='1';
            FULL<='0';
            cont<=0;
          elsif (cont /= 500) then
            cont<=cont+1;
            end if;

        end if;
end process echo;

 

 

When I tried with the same clock happened the same

 

echo: process(clk1)
begin
        if (rising_edge(clk1)) and (switch='1') then     --State1
            
            if (cont1 = 500) then   --cont1= counter of the state1
                 switch<='0';
                 FULL<='1';
                 cont1<=0;    
            elsif(cont1 /= 500) then
                 cont1<=cont1+1;

            end if;
          end if;
   
        if rising_edge(clk1) and (switch='0') then --State2
            if (cont = 500) then  --cont= counter of the state2
            switch<='1';
            FULL<='0';
            cont<=0;
          elsif (cont /= 500) then
            cont<=cont+1;
            end if;

        end if;
end process echo;

 

In this second case I can join the two rising_edge if conditions because it has the same clock. When I do that, it finally works, but it is not useful.

 

Any idea? I have lost more than 10 hours in this ****.

 

Thank you very much for your attention.

 

Óscar.

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Highlighted
Scholar
Scholar
3,213 Views
Registered: ‎02-27-2008

Re: switching 2 clocks in the same process

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o,

 

I suggest you look at the BUFGMUX primitive.  It allows you to switch between clocks without creating a runt pulse, or glitch.

 

Switching between asynchronous clocks is the most dangerous of tasks.  It at all possible, I would always use the best clock, and synchronize the results with the other clock (if needed).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Visitor
Visitor
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Registered: ‎12-12-2014

Re: switching 2 clocks in the same process

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I almost forgot, one clock works at 50 MHz and the other at 1 MHz and they are TOTALLY independent, one clock comes from an external system (1 MHz) and the other is the internal.

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Highlighted
Scholar
Scholar
3,214 Views
Registered: ‎02-27-2008

Re: switching 2 clocks in the same process

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o,

 

I suggest you look at the BUFGMUX primitive.  It allows you to switch between clocks without creating a runt pulse, or glitch.

 

Switching between asynchronous clocks is the most dangerous of tasks.  It at all possible, I would always use the best clock, and synchronize the results with the other clock (if needed).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Visitor
Visitor
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Registered: ‎12-12-2014

Re: switching 2 clocks in the same process

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After posting I made some changes in my design. As you say, I used the fast clock to 'sample' the slower one and see the edges.

if the preview sample was 0 and the new is '1' I know there is a rising edge. If the preview sample was 1 and the new is 0 I know there is a falling edge.

Is this the correct and easiest way to solve my problem?

 

Thank you very much :)

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: switching 2 clocks in the same process

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Much Better,

 

Be careful, as clock domain crossing requiresa synchronizer to prevent metastability.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
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Registered: ‎12-12-2014

Re: switching 2 clocks in the same process

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Thanks for the advice :). Now im having synchronization problems, but I think I can solve them by myself.

 

Thank you really :D

 

Óscar.

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