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naveengk14
Explorer
Explorer
4,328 Views
Registered: ‎09-16-2013

virtual clock

Hi all,

 

 

What is Virtual Clock...?

why it is used..?

 

 

Thanks
Naveen G K
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4 Replies
arpansur
Moderator
Moderator
4,324 Views
Registered: ‎07-01-2015

Hi @naveengk14,

 

Please go through page 62 of following link:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug903-vivado-using-constraints.pdf

 

also go through following link to get an idea of it's usage
http://www.xilinx.com/support/answers/55287.html

 

Thanks,
Arpan

Thanks,
Arpan
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syedz
Moderator
Moderator
4,322 Views
Registered: ‎01-16-2013

@naveengk14,

 

Check the following forum thread:

https://forums.xilinx.com/t5/Vivado-TCL-Community/About-propagated-attribute/td-p/253702

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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yashp
Moderator
Moderator
4,305 Views
Registered: ‎01-16-2013

Hi,

Virtual clocks are clocks without source objects/as name states without physical existence.

When you have any path coming outside the FPGA and without registered any data going outside the FPGA.
INPUT PAD --> Combination logic --> OUTPUT PAD so to analyze the timing you need some reference and then Virtual clocks comes into picture.

Thanks,
Yash
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arpansur
Moderator
Moderator
4,199 Views
Registered: ‎07-01-2015

Hi @naveengk14,

 

Is your query addressed?

 

If your query is addressed please close this thread by marking "Accept as solution" to the answer that addressed your query.

 

Thanks,
Arpan

Thanks,
Arpan
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