You can implement several key wireless applications including radio and wireless backhaul very efficiently using Zynq SoC devices. Radio applications are especially good examples of this, where the Zynq SoC with both on-chip processor cores and programmable logic can implement fully-integrated hardware and software systems that handle all digital front-end processing. Every wireless application has different performance requirements and needs an appropriate OS.
The radio digital front-end application is the major part of a typical Remote Radio Head (RRH) used by 4G wireless networks. Processing requirements for this application can be split into signal-processing and control-processing tasks. The control-processing side of a radio typically performs radio calibration, configuration, alarms, scheduling, and message termination from the networks. These tasks do not require high performance and are easily handled by software running on a single ARM Cortex-A9 processor core in the Zynq SoC.
In the signal-processing domain, the Zynq SoC can implement high-sample-rate filters for digital up- and down-conversion, Crest Factor Reduction (CFR), and Digital Pre-Distortion (DPD). Due to performance requirements, sample-rate conversion and CFR are best implemented using the Zynq SoC’s programmable logic (PL) section while a DPD implementation will use both the PS (Processor System) and the PL in the Zynq SoC. DPD processing can be broken down into the high-speed data path and the update path. The update path is used to periodically update filter-bank coefficients. Typically, coefficients are updated with a period measured in tens of milliseconds so this task is well-suited to being implemented as software running on one of the Zynq SoC’s ARM Cortex A9 processor cores with its embedded NEON SIMD vector computing unit.
Selecting the appropriate processing architecture for supporting both the DPD application and the control-processing application is an important decision because the choice will define the system’s overall performance, reliability, and ease of maintenance. A common architecture selected for wireless radio application is AMP (asymmetric multiprocessing) mode, which devotes an entire ARM processor core running bare-metal (no OS) code to DPD processing. This approach provides more computing headroom to meet the time requirements for updating DPD coefficients. All other applications such as control and OAM (orbital angular momentum) multiplexing run on the second ARM Cortex-A9 processor core under the control of an OS.
Because the OS only controls one of the two ARM processor cores in AMP mode, an inter-processor channel must be established between the applications running in the two separate processor cores using the OCM (on-chip memory) or shared memory, for example. This channel is especially important for some key control applications such as the one that monitors the DPD module’s health. Such IPC (inter-process communication) solutions are non-standard and must be developed separately for systems using AMP mode.
By contrast, an SMP (symmetric multiprocessing) architecture is very straightforward with a single OS instance controlling both ARM processor cores and all applications. IPC, debugging, and the supporting tool chain all run under the same OS. To ensure that sufficient processing resources are devoted to the DPD application, specific techniques such as core affinity and interrupt shielding can be applied. In the former case, the DPD application will run on one core, potentially with no other tasks sharing resources on that processor other than the OS scheduler. In the latter case, interrupt services (other than those triggered by the DPD application) are directed to the second core allowing the DPD application to fully utilize the one processor core’s resources.
With its dual-core ARM Cortex-A9 MPCore processor, Zynq SoC can support either AMP or SMP implementations.