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Free, on-demand Webinar discusses how to get 500MHz+ system speeds for FPGA-based radio (and other high-speed) designs

Xilinx Employee
Xilinx Employee
0 1 102K

Speed is the name of the game for digital radio design and for many other high-speed systems as well. No surprise there. It should also not be a surprise that there are special device features and design techniques that yield more performance—sometimes a lot more performance. If only you know what to use and how. A new on-demand Xilinx video Webinar has just been posted that gives you this knowhow and it’s free.


The Webinar is titled “How to Efficiently Implement Flexible and Full-Featured Digital Radio Solutions Using All Programmable SoCs” but don’t let the title fool you. Wireless System Architect Michel Pecot works long hours to figure out the best ways to extract maximum performance from Xilinx FPGAs and Zynq SoCs and he shares many of these design techniques and tricks with you in this 55-minute video webinar.


For example, Pecot discusses specific ways to optimize FPGA-based system implementations—starting at the architectural level—to get maximum clock rates and maximum performance with exceptional resource utilization. From the Webinar:



Sub-band splitting and multi-stage carrier mixing-extraction.jpg 


The image above shows two different architectures for handling digital up-conversion. In this example, the digital up-converter needs to process twelve 5MHz carriers over a 100MHz instantaneous bandwidth. The top part of the image shows the usual implementation approach: up-sampling each carrier to 122.88Msamples/sec and then mixing the twelve carriers together to generate a composite output. The top block diagram shows the up-sampling of twelve carriers from 30.72Msamples/sec to 122.88Msamples/sec.


The bottom part of the figure shows an architecture that first splits the twelve carriers into three 20MHz sub-bands, each containing four carriers. After up-sampling each carrier to 30.72Msamples/sec as shown in the top diagram, the four carriers in each of the three sub-bands are mixed together to generate three composite signals that are then up-sampled to 122.88Msamples/sec and finally mixed together to produce the output signal.


The two architectures in the diagram produce the same result but the second approach is much more resource-efficient: it uses 50% fewer LUTs and 60% fewer DSP48 blocks.


Among the other FPGA-specific tidbits in this free Webinar that will aid any high-performance design:



  • Multi-cycle versus multi-channel architectures
  • Optimal pipelining to maximize system clock rates
  • Using the proper operating mode to maximize pipelined BRAM performance
  • LUT compression to maximize clock rates and minimize power consumption
  • DSP48 use techniques that boost performance



Finally, Pecot specifically calls out features in the Xilinx UltraScale architecture—as implemented in 20nm and 16nm devices—that aid high-speed design:



  • Specific performance-boosting DSP48E2 improvements
  • Specific performance-boosting BRAM improvements
  • Improved on-chip routing to relieve signal congestion and boost resource utilization


As a result of these improvements, all UltraScale device speed grades can achieve and exceed 500MHz system clock rates while you need to specify mid-grade devices to achieve that performance level using Xilinx 7 series devices.


This is a taste of what you will find in this free Webinar. To register and watch, click here.

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