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How do you design backplanes for 25+ Gbps operation? Teraspeed’s Scott McMorrow tells you how in two videos

Xilinx Employee
Xilinx Employee
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Early this year, Xcell Daily visited Teraspeed Consulting’s booth at DesignCon where there was a demo setup of a 28Gbps backplane for testing. (See “28Gbps backplane demo highlights Samtec low-loss connectors using Virtex UltraScale FPGAs.”) The setup consisted of two intercommunicating Xilinx VCU109 Eval boards (based on 20nm Xilinx Virtex UltraScale VU095 FPGAs) plugged into high-speed, 20-inch backplane (24-inch total path length) through high-speed Samtec ExaMAX connectors. Teraspeed selected the Xilinx UltraScale VU090 FPGA to build the fastest possible demonstration vehicle for the Samtec ExaMAX connectors because of its clean 28Gbps SerDes transmitters and bullet-proof 28Gbps SerDes receivers. (Note: Samtec recently acquired Teraspeed Consulting.)


Teraspeed’s Scott McMorrow has just published two videos with an hour of material covering this setup and the lessons learned about the design, the materials, and the connectors needed to construct reliable backplanes that can operate above 25Gbps at the lowest possible cost. Well worth watching:











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