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In FPGA Design, Timing Is Everything

Xilinx Employee
Xilinx Employee
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By Angela Sutton, Staff Product Marketing Manager, FPGA, Synopsys and Paul Owens, Corporate Applications Engineer, FPGA, Synopsys

 

 

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimizing the design to meet timing, but also in the designer’s ability to specify goals upfront and diagnose and isolate timing problems downstream. Designers now have access to certain tips and tricks that will help you set up clocks; correctly set timing constraints using tools like Synopsys Synplify Premier; and then tune parameters to meet the performance goals of your Xilinx FPGA design.

 

There are multiple angles of attack, including:

 

  • Better design setup, such as complete and accurate timing constraints and clock specifications;

 

  • Time-saving design techniques such as careful RTL coding for better performance results and grouping together the parts of the design that pose the greatest performance challenge, to reduce iteration runtimes when you later tune the design;

 

  • Correlation of synthesis and place-and-route timing to deliver better timing quality of results (QoR) and timing closure.

 

Let’s take a closer look at some of these techniques in all three categories, and examine how to use them to achieve your timing goals.

 

 

STEP 1: BETTER DESIGN SETUP

 

The biggest bang for your buck will come from specifying correct and complete design constraints. The constraints communicate your design intent and the design’s performance goals to the synthesis tool. Once the design has been synthesized, these constraints and the critical-path information will automatically be forward-annotated to the Vivado Design Suite place-and-route (P&R) tools to further ensure that timing will be met.

 

 

STEP 2: RTL CODING STYLES AND CRITICAL-PATH TUNING

 

To converge on better timing, we recommend that you use certain coding styles for finite state machines, RAMS, math/DSP functions, clock trees and shift registers. The result will be improved timing QoR, because the synthesis tool is better able to infer an implementation using FPGA primitive building blocks.

 

Additionally, these coding styles keep you from creating unnecessary logic such as inferred latches, read/write check logic for RAMS and logic that could have been packed into a DSP primitive. While much has been written on this topic, using core-generator capabilities within your synthesis tool is a key point to consider.

 

 

STEP 3: GAINING FINAL TIMING CLOSURE

 

General timing can be reported post-synthesis and after placement and routing. For example, Synplify software allows you to report upon specific parts of the design of interest using a TCL command (report_timing). To improve timing QoR further, we recommend that you correlate post-synthesis and post-P&R timing results, specifically the slack margins for given start points and endpoints on timing-critical paths.

 

The methodology we have outlined will intercept clock and constraints setup issues early, while also offering a variety of techniques to tune and correlate timing in your design and its RTL to get fast timing closure.

 

 

 

This blog post was adapted from the recent Xcell Journal article titled “In FPGA Design, Timing Is Everything.” For much more in-depth technical information about this topic, see this article in the latest issue of Xcell Journal. Click here to read it online or download the PDF.

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