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Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

Xilinx Employee
Xilinx Employee
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By Adam Taylor


Over the last few blogs in this series, I have focused on the private timers and watchdogs available within the Zynq All Programmable SoC’s processor system (PS). The Zynq SoC’s PS also incorporates two triple timer counters (TTCs), which provide a far more flexible timing resource. You can use these TTCs as timers or to output waveforms on the Zynq SoC’s EMIO or MIO pins. The diagram shown below, taken from the Zynq SoC Technical Reference Manual (UG585)—shows the architecture of each TTC and how they are independent of each other.


Zynq TTC Diagram.jpg 


What the diagram does not clearly show however, is that each of the pre-scalers can be clocked by the processor clock or through the programmable logic via signals from the Zynq SoC’s EMIO or MIO pins. The clock source for each TTC is selectable via the Clock Control register (see below).



You can use a TTC as a more capable timer or as a scheduler that generates different interrupts at specified count values. You can also use the TTC to generate waveforms with set duty cycles. The most basic example of such a waveform would be to toggle a LED to show that the processor is operational and is running the application code. What makes the TTC very flexible is its ability to generate a PWM (pulse-width-modulated) output. Embedded systems use PWM output signals for a number of applications including industrial motor control. PWM control offers the embedded designer a number of advantages including noise immunity.



As many industrial systems use PWM for communication (e.g. in older smart meters between sensors or instruments), the Zynq SoC’s TTCs also provide the ability to receive and count a PWM signal (in processor clock cycles); the event timer can be configured to count the number of processor clock cycles during the period when an external clock signal is high or low.



There are three timer/clock units within each of the Zynq SoC’s two TTC instantiations. Each TTC has the following registers:



Clock Control : Defines the TTC’s clock source, pre-scale value, and the clock edge to be used.



Counter Control : Defines the generated waveform settings, the timer mode, the count direction, enables the match value and interval interrupts, resets the counter, and disables controls.



Counter Value :  A read only register containing the current value of the timer.



Interval Counter : A intermediate value used in the interval mode as the value that is counted to or from depending upon the count direction (up or down).



Match Counter (three registers):  When the match registers are enabled, separate interrupts are generated when the counter value equals the values stored in these registers.



Interrupt Register : Defines the status of the six interrupts controlled by the TTC. Permissible interrupts are Match 1, Match 2, Match 3, Internal, Overflow, and Event.



Interrupt Enable :  Enables the TTC interrupts.



Event Control Timer : Enables the timer, resets the timer, specifies the clock phase for counting, and specifies how the timer handles overflow conditions.



Event Register :  Contains the value of the internal counter at the end of the counting phase for an external pulse. Used to measure an external pulse width using the CPU clock as a counting reference.



Each TTC has two basic modes of operation: interval or overflow mode, plus the event timer.



Interval mode : The counter counts to a value contained within the interval register, counting either up or down, and generates an interval interrupt whenever the count reaches zero (when enabled).


Overflow mode : The counter increments or decrements from 0 to full scale. When the counter wraps around, the TTC generates an overflow interrupt.


In both of these modes, match interrupts will be generated when the counter equals the values within the match registers (if enabled).


The TTC uses the count value contained within the Match Count 1 register to generate a waveform with the required duty cycle in both the interval and overflow modes. When the counter value equals the values stored in the Match Counter 1 register, the waveform being output will toggle from either 1 to 0 or 0 to 1 depending upon the setting of the waveform polarity bit within the counter control register. The waveform again inverts its state upon the generation of either the interval or overflow interrupt, depending upon the selected timer mode.


The event timer can be used only with an external source and is a resource you can use to measure an event’s duration or to decode a PWM signal.


In the next blog post in this series, we will look at examples of using the TTC.



Please see the previous entries in this MicroZed series by Adam Taylor:


The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16


Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15


MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14


More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13


MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12


Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11


Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10


Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9


MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8


Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7


A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 


Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5


Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4


Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3


Adam Taylor’s MicroZed Chronicles: Setting the SW Scene


Bringing up the Avnet MicroZed with Vivado



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