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Is Opal Kelly’s SYZYGY the new "Goldilocks" high-speed, mezzanine-board and peripheral I/O standard?

by Xilinx Employee ‎08-14-2017 11:41 AM - edited ‎08-14-2017 11:43 AM (30,770 Views)

 

Today, Opal Kelly announced the SYZYGY open I/O standard, designed to connect peripheral devices and mezzanine boards to the high-speed SerDes ports of FPGAs and SoCs like the Zynq SoC and Zynq UltraScale+ MPSoC. The SYZYGY standard sits somewhere between the inexpensive, low-performance Pmod interface and the higher-pin-count, high-speed FMC interface standard in both speed and cost. In creating the SYZYGY open standard, Opal Kelly is shooting for a “Goldilocks” I/O standard that’s “just right.”

 

From today’s announcement:

 

 

“The SYZYGY specification defines two connector types: the Standard SYZYGY connector offers up to 28 single-ended, impedance-controlled signals, 16 of which may be defined as differential pairs for interface standards such as LVDS. The Transceiver SYZYGY connector boasts four lanes of Gigabit-class transceiver connections and also offers up to 18 single-ended signals. The Transceiver connector is intended for use with JESD204B data acquisition, SFP+ transceivers, and other devices requiring high-speed SERDES. Both Standard and Transceiver connectors have optional low-cost, high-performance coaxial or twinaxial cable assemblies…

 

“SYZYGY is intended to fit the sweet spot of peripheral connectivity between the existing low-performance, low pin-count [Digilent] Pmod and the expensive, high-performance ultra-high pin-count of FMC,” said Jake Janovetz, President of Opal Kelly Incorporated. “We envision SYZYGY occupying the space between present standards where pin economy, low cost, and high performance converge. Carriers could offer multiple connectivity options to provide additional flexibility to system implementers…

 

“Opal Kelly will release their upcoming SYZYGY Compatible carrier, the Hub, an open-source board incorporating a Xilinx Zynq SoC. As an open-source hardware design, the Hub will serve as a SYZYGY reference platform for adopters and manufacturers. Opal Kelly also plans to add SYZYGY support to several future FPGA integration products.”

 

 

Here’s a preview photo of Opal Kelly’s SYZYGY-compatible Hub carrier board based on the Xilinx Zynq SoC. The Hub board has four SYZYGY ports on its periphery, marked Ports A,B, C, and D in the photo.

 

 

Opal Kelly Syzygy-HubPhoto.jpg

 

Opal Kelly’s Hub, a SYZYGY-compatible carrier board based on the Xilinx Zynq SoC

 

 

 

The SYZYGY Standard connectors are Samtec 40-pin QTE/QSE connectors with 0.8mm pin pitch. The The SYZYGY Transceiver connectors are Samtec 40-pin QTH-DP/QSH-DP connectors with 0.5mm pin pitch. The Transceiver connectors are optimized for differential-pair signaling, as you can see from this drawing:

 

 

Opal Kelly SYZYGY Connectors.jpg

 

SYZYGY Standard (top) and Transceiver (bottom) Connectors

 

 

Samtec also provides pre-assembled cables for these connections: EQCD-020 impedance-controlled cables for the Standard SYZYGY interface and HQDP-20 twinax differential cables for the Transceiver SYZYGY interface.

 

Here’s a graph of throughput versus pin count for various I/O standards and protocols to give you an idea of where the SYZYGY I/O standard fits in the I/O spectrum:

 

 

Opal Kelly SYZYGY IO Performance vs Pin Count Chart.jpg 

 

 

 

You’ll find the SYZYGY specification here.

 

Please contact Opal Kelly directly for more information about the SYZYGY I/O standard and the Zynq-based Hub board.