As FPGAs get bigger, many systems start to fit into just one programmable device.
But not all.
For a variety of reasons, some really large systems must still be implemented with multiple devices, which elevates the system-level importance of efficient, fast chip-to-chip interconnect. With the rise of multi-Gbps SerDes ports, the scalable Interlaken protocol has become a de facto standard for chip-to-chip interconnect over the past decade, especially in the networking arena. Xilinx has supported the use of the Interlaken protocol over multiple FPGA generations, previously as a soft core. All Virtex UltraScale devices and some Kintex UltraScale devices now incorporate multiple embedded hard 150Gbps Interlaken IP cores—using 12x12.5Gbps or 6x25Gbps lanes—which makes it even easier for you to use this efficient, highly standardized chip-to-chip protocol.
The following 4-minute video gives you a quick overview of this aspect of the UltraScale architecture. The video in the demo shows a Virtex UltraScale VU095 All Programmable device mounted on a VCU107 Eval Board running 12 Interlaken lanes at 12.5Gbps for an aggregate peak bandwidth of 150Gbps using only 12 differential pairs. Here’s a block diagram of the system in the demo:
The Virtex UltraScale VU095 FPGA has six on-chip, low-latency Interlaken cores but the demo in the video only uses one. Here’s the video: