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Panoradio: an open-source, Zynq-based, direct-sampling SDR with 100MHz of bandwidth reaches from dc to VHF

Xilinx Employee
Xilinx Employee
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The November/December 2017 issue of the ARRL’s QEX magazine carries an article written by Stefan Scholl (DC9ST) titled “The Panoradio: A Modern Software Defined Radio with Direct Sampling.” This article describes the implementation of an open-source software-defined radio (SDR) based on an Avnet Zedboard—which in turn is based on a Xilinx Zynq Z-7020 SoC—and an Analog Devices AD9467-FMC-250EBZ board based on the 16-bit, 250Msamples/sec AD9467 ADC.

 

 

 

Panoradio.jpg 

 

 

Stefan Scholl’s Panoradio SDR is based on a Zedboard (the green board on the left, with a Zynq Z-7020 S0C) and an AD9467-FMC-250EBZ ADC board (the blue board on the right)

 

 

 

The Panoradio’s features include:

 

  • 0 -100 MHz direct sampling reception
  • Direct sampling of 70 cm (425 – 440 MHz) signals
  • Three independent, zoomable waterfall displays (100 MHz to 6.1 kHz bandwidth)
  • Two independent audio receivers (22 kHz bandwidth) with Weaver SSB demodulation
  • Standalone operation (no PC needed)
  • Runs full Linux stack including demodulation software (e.g. Fldigi)

 

Beyond the comprehensive design, Scholl’s article contains one of the most concise arguments for the adoption of SDRs that I’ve seen:

 

“The extensive use of digital signal processing has many advantages over analog circuits: Analog processing is often limited by the laws of physics, that can hardly be overcome. Digital processing is limited only by circuit complexity—a better performance (sensitivity, dynamic range, spurs, agility, etc.) is achieved by more complex calculations and larger bit widths. Since semiconductor technology has continuously advanced following Moore’s Law, very complex systems can be built today and it is possible to achieve extraordinary accuracy and performance for digital signals with comparatively little effort.”

 

Scholl then lists numerous SDR advantages:

 

  • Digital FIR filters can be built with virtually any filter response.
  • Mixers and amplifiers implemented with digital multipliers do not introduce spurs, harmonics, or unwanted IMD (inter-modulation distortion). Gain imperfection or other parasitic behaviors are also absent.
  • Digital oscillators based on direct digital synthesis (DDS) achieve extremely high spectral purity with virtually no spurs or harmonics.
  • Digital oscillator frequency can change instantaneously without phase discontinuity.
  • DSP is impervious to component aging effects, impedance mismatch, and a variety of EMC issues that plague analog circuitry.
  • Only quantization noise is present and can be made arbitrarily low by increasing bit widths.
  • SDRs are easily copied and can be backed up prior to making changes so that failed experiments can be easily reversed.

 

 

The Panoradio’s DSP section consumes less than 50% of the Zynq Z-7020 SoC’s PL (programmable logic) resources. As Scholl writes: “This quite low utilization would allow for even more complex DSP.” Note that is the resource utilization in a low-end Zynq SoC. There are several Zynq SoC family members with significantly more PL resources available.

 

At the end of the article, Scholl writes: “Interestingly, the bottleneck is not the FFTs or the communication with the IP cores, but the drawing routines for the waterfall plots. The Zynq does not have any graphics acceleration core, which could speed up the drawing process. However, Xilinx has realized this bottleneck and included graphics acceleration in the Zynq successors: the UltraScale MPSoC, and the Zynq UltraScale+.”

 

(Actually, there’s just one device family here, the Zynq UltraScale+ MPSoC, with Mali-400 GPUs in the EG and EV variants, but Scholl will no doubt be even more interested in the new Zynq UltraScale+ RFSoCs, which incorporate 4Gsamples/sec ADCs and 6.4Gsamples/sec DACs—perfect for SDR applications.)

 

For more information on the Zynq UltraScale+ RFSoC, see:

 

 

 

 

 

 

 

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