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RS-FECs for 100Gbps communications: Trade a little bandwidth for a big BER reduction

Xilinx Employee
Xilinx Employee
0 0 49.6K

“At data rates above about 10 Gbits/s, the frequency response and impedance mismatches from the transmitting end of one SERDES (serializer-deserializer) to the receiving end of another SERDES causes eye-closing ISI (inter-symbol interference). The combination of pre/de-emphasis at the transmitter and equalization at the receiver fixes enough of that ISI to reopen the eye so it can operate at a reasonable BER (bit error ratio). The receiver usually employs two types of equalization: CTLE (continuous time linear equalization) at its input and DFE (decision feedback equalization) that feeds back ISI corrections following identification of 1s and 0s by the decision circuit.”

 

That’s how Ranson Stephens EDN article “Why FEC plays nice with DFE” starts out. This readable article discusses the use of RS-FECs (Reed-Solomon Forward Error Correction) to trade off a bit of bandwidth for a big BER reduction—especially handy when dealing with high-speed serial communications like 100G Ethernet.

 

For more information on RS-FECs, see “Xilinx Announces Availability of 100G RS-FEC IP for Data Center, Service Provider, and Enterprise Applications” and “RS-FEC in Virtex UltraScale FPGA operates Finisar 100G ER4f CFP4 optical module error-free over 50km of fiber.”