UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 

Swipe these Low Cost FPGA-based MIPI DSI and CSI-2 Interfaces for Video Displays and Cameras

Xilinx Employee
Xilinx Employee
0 0 74K

MIPI’s DSI (Display Serial Interface) and CSI-2 (Camera Serial Interface 2) have become industry-standard, low-cost interfaces to video displays and cameras across a wide variety of embedded systems and you can now connect Xilinx FPGAs to these low-cost devices and other MIPI-compatible ASSPs using these interfaces in high-bandwidth applications supporting 4K2K and beyond. Even better, the free Xilinx App Note XAPP894 shows you how to do this in great detail. This App Note published late last month is a follow-up to the IEEE Webinar and working demo discussed last March in a previous Xcell Daily blog. (See “How to Drive Multiple Live Cameras and Displays for Pennies—A Free IEEE Spectrum webinar.”)

 

Both the DSI and CSI-2 MIPI interface standards use the MIPI D-PHY and FPGAs do not yet have I/O that natively supports D-PHY. You can implement the D-PHY hardware specification with discrete components outside the FPGA however and XAPP894 shows you how to adapt and FPGA’s LVDS transmitters and receivers using two different approaches: compliant and compatible. For proprietary designs and cost-optimized systems, full compatibility and/or the highest performance might not be required as long as the D-PHY specifications are met and the link is robust under all conditions. A low-cost resistor network for transmission and reception is sufficient to fulfill the design requirements in such cases. This is the compatible solution. These solutions will work with Xilinx 7 series FPGAs, Zynq-7000 All Programmable SoCs, and Spartan-6 FPGAs.

 

The resistor network for transforming an LVDS transmitter into a compatible D-PHY transmitter looks like this:

 

 

D-PHY Compatible Transmitter.jpg

 

 

The resistor network for transforming an LVDS receiver into a compatible D-PHY receiver looks like this:

 

 

D-PHY Compatible Receiver.jpg

 

Designs requiring full MIPI compliance and/or the highest possible performance can use active, external PHY components. This setup is the compliant solution and XAPP894 provides details for MIPI-to-FPGA and FPGA-to-MIPI designs.

 

For both the compatible and compliant solutions, logic that functions as the MIPI D-PHY’s lane-control logic can be implemented inside the FPGA. XAPP894 has a block diagram showing what that might look like:

 

 

 MIPI D-PHY Block Diagram.jpg

 

 

 

XAPP894 also provides some pcb layout guidelines and recommendations to ensure that your D-PHY implementation doesn’t suffer from pcb-induced problems.

 

Finally, you might ask “Does it work?” (That's the polite way of asking "Is this a dry lab?") Here’s a video from last March to confirm that, yes indeed, it works: