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Ultra HD H.264 Video Codec IP runs on Zynq Z-7045 SoC

Xilinx Employee
Xilinx Employee
0 0 42.6K

 

Anand V Kulkarni, Engineering Manager, Atria Logic India Pvt Ltd, Bangalore, India

 

 

Atria Logic’s H.264 codec IP blocks (the AL-H264E-4KI422-HW encoder and the AL-H264D-4KI422-HW decoder) achieve UHD 4k@60fps video with each running on a Xilinx Zynq Z-7045 SoC as shown in the figure below.

 

 

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Block Diagram of Atria Logic UHD H.264 Codec Solution

 

 

Atria Logic’s AL-H264E-4KI422-HW is a hardware-based, feature-rich, low-latency, high-quality, H.264 (AVC) UHD Hi422 Intra encoder IP core. The AL-H264E-4KI422-HW encoder pairs with the Atria Logic AL-H264D-4KI422-HW low-latency decoder IP.

 

The IP cores’ features include:

 

 

  • Complete modular implementation that you can customize and scale
  • 264 Intra-only Hi422 Level 5.1 encoder and decoder
  • Integrated HDMI2.0 receiver and transmitter subsystems
  • 8/10-bit support
  • YUV 4:2:2/4:4:4, RGB support
  • Very low latency at ~0.3sec
  • Variable bit rate (VBR) and constant bit rate (CBR) support
  • Video quality at 0.99% SSIM, or 50dB PSNR or higher
  • Video processing subsystem for pre/post processing including color-space conversion, video, scaling, and chroma subsampling
  • Gbps Ethernet streaming output support

 

 

When devising a plan for evaluating our UHD Encoder and Decoder IP cores and to meet 4K@60fps performance requirements, we needed a flexible, powerful platform. We settled on the Xilinx ZC706 evaluation kit based on the Zynq Z-7045 SoC because:

 

 

 

 

  • The Zynq Z-7045 SoC’s programmable logic can accommodate the encoder and decoder IP logic while meeting our stringent timing requirements to achieve the required performance.

 

  • The Zynq SoC’s processing system with its dual-core ARM Cortex-A9 MPCore processor gave us the ability to modify application driver software and to build customizations like an application-specific GUI.

 

 

The H.264 encoder supports the H.264 Hi422 (High-422) profile at Level 5.1 (3840x2160p30) for Intra-only coding. Support for 10-bit video content means that there is no grayscale or color degradation in terms of banding. Support for YUV 4:2:2 video content means that there is better color separation—especially noticeable for red colors—which makes images appear sharper. These video-quality attributes are especially important for medical-imaging applications.

 

 

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Atria Logic UHD H.264 Encoder IP Block Diagram

 

 

Support for Intra-only encoding allows the H.264 encoder to operate at frame-rate latencies. A macroblock-line-level pipelined architecture further reduces the latency to the sub-frame level: about 0.3msec. Using a pipelined design that processes 8 pixels/clock allows the design to encode 4k@60fps in real time.

 

Implementation of the Atria Logic H.264 encoder consumes only 78% of the Zynq Z-7045 SoC’s programmable logic and DSP resources and 55% of the available RAM, leaving ample room for other required circuitry.

 

The H.264 decoder supports the H.264 Hi422 (High-422) profile at Level 5.1 (3840x2160p30) for Intra-only coding. As with the encoder, support for 10-bit video content means that there is no grayscale or color degradation in terms of banding. The decoder also supports YUV 4:2:2 video content. Support for Intra-only decoding using a pipelined architecture allows the decoder to operate at frame-rate latencies.

 

 

 

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Atria Logic UHD H.264 Decoder IP Block Diagram

 

 

Low latency is important for any closed-loop man/machine application. When the Atria Logic AL-H264E-4KI422-HW encoder is connected to the Atria Logic AL-H264D-4KI422-HW low-latency decoder via an IP network, the glass-to-glass latency is about 0.6msec (excluding transmission latency). That’s about a 2-frame latency.

 

An efficient implementation of the Atria Logic H.264 decoder only takes up 68% of the Zynq Z-7045 SoC’s programmable logic resources, 35% of available DSP resources, and 45% of the available RAM, leaving ample room for implementation of any other required circuitry.

 

The design’s HDMI subsystem consists of two major modules: the Xilinx LogiCore HDMI TX and RX subsystems, configured as shown in the figure below:

 

 

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The HDMI Transceiver (GTX) module transmits and receives the serial HDMI TX and RX data and converts between these serial streams and on-chip parallel data streams as needed. The transceiver module, which converts parallel data into serial and vice versa, employs the Zynq SoC’s high speed GT transceivers as the HDMI PHY.

 

The TX subsystem consists of the transmitter core, AXI video bridge, video timing controller, and an optional HDCP module. An AXI video stream carries two or four pixels per clock into the HDMI TX subsystem and supports 8, 10, and 12 bits per component. This stream conforms to the video protocol defined in the Video IP chapter of the AXI Reference Guide (UG761). The TX subsystem’s video bridge converts the incoming video AXI-stream to native video and the video timing controller generates the native video timing. The audio AXI stream transports multiple channels of uncompressed audio data into the HDMI TX subsystem. The Zynq Z-7045 SoC’s ARM Cortex-A9 processor controls the HDMI TX subsystem’s transmitter blocks through the CPU interface.

 

The HDMI RX subsystem incorporates three AXI interfaces. A video bridge converts captured native video to AXI streaming video and outputs the video data through the AXI video interface using the video protocol defined in the Video IP chapter of the AXI Reference Guide (UG761). The video timing controller measures the video timing. Received audio is transmitted through the AXI streaming audio interface. A CPU interface provides processor access to the peripherals’ control and status data.

 

The HDCP module is optional and is not included in the standard deliverables.

 

 

 

 

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