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White Rabbit module for NI’s cRIO based on Spartan-6 FPGA: One clock makes you faster and one clock makes you slow

Xilinx Employee
Xilinx Employee
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Many distributed networks including those used for 5G communications, power-grid monitoring, and particle physics research need precise time synchronization among the distributed network nodes. CERN’s White Rabbit Ethernet protocol is designed to provide sub-nanosecond accuracy while synchronizing more than 1000 network nodes connected via either fiber or copper. As reported at a status update meeting a week ago, the University of Zürich has developed a plug-in White Rabbit module for National Instrument’s CompactRIO (cRIO) control and monitoring system based on a low-end Xilinx Spartan-6 FPGA  and it has been tested by EN-ICE group in CERN’s Engineering Department. Here’s an annotated photo of the board:

 

 

CERN White Rabbit Module for NI cRIO.jpg

 

 

The module connects to the network via its optical SFP port and generates disciplined reference clocks that are used by the rest of the local node for network timing synchronization. With the Spartan-6 FPGA clocking at 160MHz, no output clock jitter was detected in the latest design tests.

 

 

Prior Xcell Daily coverage of CERN’s White Rabbit protocol:

 

 

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