UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Adam Taylor’s MicroZed Chronicles, Part 104: XADC with Real World Signals

by Xilinx Employee ‎10-12-2015 10:41 AM - edited ‎01-06-2016 11:21 AM (14,631 Views)

 

By Adam Taylor

 

 

So far in the series, we have used the Zynq SoC’s XADC to read data from temperature and voltage sensors on chip. But imagine that we want to actually use the XADC to read in an analog signal and to process that information. We’ll look at how we can perform this sort of task over the next few blogs.

 

First, there are a few things we need to think about and address to get maximum performance. As I mentioned last week, we need to interface with the XADC using an AXI interface.

 

Here we have options. We can connect with an AXI4-Lite interface or we can add an AXI streaming interface if we wish to add further signal processing like a FIR filter, etc. If we do choose to add a streaming interface, XADC control and status information still flows over the AXI4-Lite interface.

 

However, in addition to deciding how we communicate with the XADC within our system, we must also consider the following:

 

  • FPGA input pin usage – Do we use the VP/VN inputs dedicated to the XADC or the Auxiliary analog inputs?
  • How do we want to configure the sampling rate of the XADC for the application?
  • Understand the settling time of the XADC and ensure that we have correctly defined the AAF (Anti-Aliasing Filter) requirements to meet settling-time requirements.
  • Should we configure the XADC for single-channel operation to maximize XADC performance?
  • Should we configure the single channel for unipolar or bipolar operation?

 

The first choice to make is the selection of the input pins for the XADC. The XADC has two dedicated differential input pins, Vp and Vn, which can be used to sample analog signals. There are also 16 auxiliary inputs that you can use. However, these auxiliary inputs have a lower FRBW (Full-Resolution Bandwidth) of 250kHz while the dedicated inputs have an FRBW of 500kHz. Therefore, if we want to be working with signals near the XADC’s maximum Nyquist frequency, we need to use its dedicated inputs. If there is more than one signal to sample, then we can use an external multiplexer. However this option will reduce the input signals sample rate.

 

The XADC can sample a channel at up to 1Msamples/sec. The DRP clock determines the actual sample rate. In an AXI instantiation, the DRP clock is directly connected to the AXI CLK. An XADC conversion requires 26 clocks so we need to carefully select the DRP clock frequency to achieve the 1Msamples/sec rate as demonstrated below. Note, we also need to ensure that the FCLK from the Zynq SoC’s PS side can generate the required frequency.

 

 

 

Image1.jpg

 

 

When using a 100 MHz bus

 

 

 

Image2.jpg

 

 

When using a 104 MHz Bus

 

 

 

To ensure we get the maximum performance out of the XADC we need to understand its settling time. The XADC can be seen as a switched capacitor input, commonly used in many ADCs based on successive approximation. As such, we need to ensure that the voltage across the XADC’s input capacitor has settled to its final value before the XADC samples the voltage. As the XADC has 12-bit resolution, we need the voltage across the capacitor to settle to within ½ LSB of a 12-bit value.

 

The architecture of the XADC allocates 75% of the sampling period for settling time as the acquisition and conversion occur in parallel. This means for a 1Msamples/sec sample rate, there is 750nsec available for the XADC’s input capacitor to settle to its final value. Ensuing we are within the settling time requires that we understand both the XADC input structure and any AAF that we implement on the board.

 

To calculate the settling time we use the following equation

 

 

Tsettle = 9.01 x 2R x C (Equation One)

 

 

Note, the resistance in the equation is 2R due to the differential input and 9.01 is the number of time constants required for the capacitor to settle to the required accuracy.

 

For the XADC, internal R = 10 kΩ and C = 3pF, making the settling time 540nsec, which is much less than the 750nsec settling time available at the fastest sampling rate. The XADC’s available settling time is always 75% of the actual sampling rate, so as we slow down the conversion rate we get more settling time. However we need to ensure that any external AAF also does not adversely affect the settling time and therefore the conversion performance.

 

We can determine how to scale our AAF using the equation:

 

 

Equation 2.jpg

 

 

As we know the maximum permissible settling time (750nsec) and the settling time of the XADC (540nsec), we can calculate the requirements for the AAF settling time:

 

 

Equation 3.jpg

 

 

Once we know the resultant time available, we can rearrange Equation One above to determine the RC constant:

 

 

Equation Four.jpg

 

 

Thus for a 1Msamples/sec system, the AAF must have a time constant of 57.77nsec. By comparison, the AAF on the ZedBoard XADC interface has a settling time of 1.802 microseconds.

 

To date all the previous examples have been based around using the sequencer built into the Zynq SoC’s XADC. The sequencer loops around the external ADC inputs and the internal sensors. As such, when we use the sequencer we get a reduced update rate between samples making it impossible to sample all channels at 1 Msamples/sec in parallel. If we are sampling simple system parameters, this limitation does not have a large effect on the system. Putting more channels in the sequence increases the time between updates but the resulting per-channel update rate will still be fast enough for most telemetry applications.

 

When we want to capture a signal that requires continuous sampling at up to 1 Msamples/sec, we need to configure the XADC to sample a single channel.

 

When we set the XADC for single-channel operation, we can also configure the input type as either a unipolar (default) or bipolar input as below. We can also extend the acquisition time from 4 to 10 clock cycles using the function:

 

 

Image3.jpg

 

 

With this introduction complete, we will begin to use the XADC next week. I will generate a simple example that uses the Zynq SoC’s Fast Interrupt from the PL to the PS to capture a signal using the Zynq SoC’s XADC and the ZedBoard.

 

 

Files, as always, are on my github repository.

 

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 MicroZed Chronicles Second Year.jpg

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

 

 

 

 

Labels
About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.