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Adam Taylor’s MicroZed Chronicles, Part 107: Combining XADC and Interrupts with Real-World Signals

by Xilinx Employee ‎11-10-2015 09:43 AM - edited ‎01-06-2016 11:00 AM (81,870 Views)

 

By Adam Taylor

 

Now that we have determined the latency from interrupt assertion to ISR execution on the Xilinx Zynq SoC, we can define the hardware we want to pull into SDSoC from Vivado. Knowing and designing for the latency means we can be sure that we never miss an XADC sample. If we had been unable to determine the latency, we would have been forced to develop a more complicated acquisition architecture in Vivado. Luckily, we have significant margin.

 

Recall that in blog 104 in this series, we examined XADC use in the real world. You will remember that we can sample at 961.5385Ksamples/sec using a 100MHz AXI clock frequency. That means a new sample and corresponding interrupt will occur every 1.04 Microseconds. It is therefore simple to show that we have sufficient margin given the measured ISR latency. (Between you and me, I was pretty confident we’d be OK but actually measuring the timing helps when we look at more complex designs.)

 

Our next step is to create our base design using Vivado. To do this, I will remove the first timer and substitute an XADC component. I will leave the second AXI Timer in place. These timers are very useful things to have in our embedded systems.

 

In the system shown below, I have connected the ip2intc_irpt signal from the XADC to the Core0_nIRQ private interrupt of core 0. This means the interrupt is only seen by the first core and not the second as it is connected to a private peripheral interrupt.

 

 

Image1.jpg

 

 

 

I inted to use the dedicated Vp / Vn input signals and not the auxiliary inputs. We can easily put these into the design by right clicking on the Vp_Vn port on the XADC and selecting “make external.” This step adds the port as you see above. These are dedicated pins. Rather helpfully, you do not need to create an XDC constraints file to define their location.

 

At this point we can build the hardware and generate the bit file. I also want to double check that the hardware is going to function correctly. With this in mind, I exported the hardware to SDK and wrote a simple program that captures the input signal. I wanted to be sure I had no issues before we pull the design into SDSoC.

 

I’ve made the code for this instalment available on the GitHub repository. As we want to talk to the XADC over the AXI interface and not the DevC interface (see blog 62 ) we use the Sysmon.h drivers. The code performs the following steps:

 

  1. Initialize the XADC using the Sysmon drivers
  2. Set the sequencer to single-channel mode
  3. Set the single-channel parameters for the Vp/Vn input channel: unipolar mode, not event driven, standard acquisition, number of cycles
  4. Clear the alarms
  5. Apply the calibration
  6. Enable an interrupt to occur at the end of the conversion—not sequence—because for a single channel, there is no sequence.
  7. Capture 64 samples from the XADC; disable interrupts; output the 64 samples over the Stdout channel

With this completed I connected a Digilent Analog Discovery module to the XADC Vp / Vn pins, which are broken out on the ZedBoard J2 pins 1 (Vn – GND) and 2 (Vp – Signal). You can see schematic of the pinout below and a picture of the MicroZed board and Analog Discovery Module on my desk.

 

 

Image2.jpg

 

Image3.jpg

 

 

 

The first thing to do was check that the sampled value output from the XADC was correct. In this case, the XADC is configured as unipolar, so for 0v input we should get an XADC value of 0x000 and for 1.0V (the maximum input value) we should get a value of 0xFFF. Between the two extremes of course it should be linear.

 

With the expected behavior confirmed, the next step was to configure the Analog Discovery module to output a sine wave and capture that signal with the XADC. The results appear below:

 

 

Image4.jpg

 

 

 

This waveform proves the hardware build is correct and that we will not be wasting time creating an SDSoC platform.

 

 

 

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 MicroZed Chronicles hardcopy.jpg

 

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 MicroZed Chronicles Second Year.jpg

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

 

 

 

Comments
by Visitor jayasankarvn
on ‎03-30-2017 09:59 PM

Dear Adam Taylor,

Thank you very much for describing the step by step procedure for interfacing analog signals through XADC. It is clearly mentioned in the user manual that total 17 analog differential channels can be connected with Zedboard. But using xadc header I can connect only 3 differential signals (Vp/Vn , vauxp0/vauxn0 and vauxp8/vauxn8). My doubt is, how to connect those remaining auxiliary channels ? How do I access the pins ? Is it necessary to use an FMC breakout board to access the remaining auxiliary channels ?

by Observer taylo_ap
on ‎03-31-2017 11:49 AM

Hi 

Thanks for reading the series, you are correct the Zynq can interface with up to 17 differential analogue signals (one dedicated Vp/Vn pair and 16 auxillary inputs shared with logic pins) 

 

The Zed board AMS header however only provides access to the Vp/Vn pair and two additional auxillary input (channels 0 and 8). As the auxillary AMS pins are shared with the logic IO you can see the remainder if you look at the Zedboard schematic Page 9 Bank 35. If you wanted to access these you would need to use a break out board which connected to the FMC connector. 

 

If you wanted to access to 16 outputs and use the Vp/Vn you could configure the XADC to use the external Mux 

 

Hope this helps 


Adam 

by Visitor se31berg
on ‎06-02-2017 05:45 AM

Hello Again

 

I just wanted to double check the connections from the XADC header to the Analog discovery. Do I just connect the yellow (waveform generator) and Black (ground) into J1 and J2 of the XADC header? Also this is my first time using Waveforms and I was wondering how to regenerate the signal that you have above. Are there specific settings that you had to choose in Waveforms?

 

Thanks!

by Visitor lucileklang
on ‎07-05-2017 02:37 AM

Hi,

I'm trying to follow this tutorial to implement a filter on the FPGA with analog audio. I have a microzed board with a breakout carrier board. 
I created the same design on Vivado and exported it on SDSoC.
You put the pins to connect for the Zedboard, but the microzed doesn't have special pins for XADC, or am I wrong ? How can I know which pins to connect and how to get the data from those pins ?

Thank you

 

 

 

by Observer taylo_ap
on ‎07-05-2017 10:59 AM

lucileklang

 

The dedicated XADC and the auxilliary XADC input pins are broken out over the connectors JX1 and JX2 you will need a board to break them out either the IOCC or a custom one you have designed.

 

Of course while you cannot inject a signal externally into the Microzed without a breakout board you can still access the on chip voltages and temperatures using it 

 

Thanks 

 

Adam 

by Observer taylo_ap
on ‎07-05-2017 11:01 AM

lucileklang

 

You will need a breakout board as on the microzed both dedicated XADC pins and the Auxillary XADC pins are all broken out over JX1 and JX2 if you check the microzed schematics you can see which pins you need to break out 

 

Thanks 


Adam 

by Visitor lucileklang
on ‎07-10-2017 02:56 AM

Hi,

 

Thanks for your help, I found the pins I needed.

Although I still have some problems : I copied your design on Vivado and tried to test the SW launched on SDSoC, it compiles but nothing happens, it doesn't print anything or get any signal... I tried to test the design with some helloworld application but it doesn't print "Hello World" either.

I also tried to compare this design with the one that you published in Part 43, that I also copied and that works fine and prints everything. I tried to see if I missed something but I can't see what's wrong.diagram ADC evolved.PNG
Could you maybe take a look and tell me if anything is wrong ?

by Observer taylo_ap
on ‎07-10-2017 11:11 AM

 lucileklang

 

Drop me an email to adam@adiuvoengineering.com and I will take a look at it, I need more info than what you have posted and this is not the right forum 

 

Adam 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.