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Adam Taylor’s MicroZed Chronicles, Part 115: A Deep Dive into the Embedded Vision Development Kit

by Xilinx Employee ‎01-18-2016 09:53 AM - edited ‎01-18-2016 09:56 AM (28,884 Views)

 

By Adam Taylor

 

 

Having assembled the Avnet MicroZed Embedded Vision Development Kit based on the Xilinx Zynq SoC and loaded up the demo boot file, the next step is to examine the demo application program in more detail. Understanding this demo program allows us to develop our own applications and understand where we can best add in the functionality we require for our applications.

 

The first step in understanding this demo is to follow the instructions contained within the PDF included with the demo boot file. This document walks you through the steps needed to download the correct files from the github repository and to build the design using the TCL shell and Vivado HLx. Once the design has been built, we can open it using the Vivado GUI and explore the block diagram. The information from Avnet is very easy to follow (you can find the instructions here) so I will not reproduce them in this blog post.

 

The simple block diagram presented within the Avnet documentation abstracts the real and much more complicated block diagram produced by Vivado for this design, as shown below:

 

 

Image1.jpg

 

Simple Block Diagram of the Demo

 

 

Image2.jpg

 

Reality of the implementation

 

 

Delving deeper into the block diagram, we can see that video path is fairly straightforward. The steps consist of decoding the received image from the imaging device, converting it into an AXI Stream, and then preparing it for output over the HDMI link. Apart from the initial input and the final output stage, all communication between modules is performed using the AXI Streaming protocol. The Video Timing Controller regenerates video system timing prior to the final output, which converts the AXI stream back into a video output.

 

Where the design gets very interesting is how the modules are connected to the Zynq PS (Processor System). When we look at the AXI bus structure we see that the Zynq PS has multiple connections to modules and uses both the Master GPIO AXI interface and the Slave HP0 AXI interface. The configuration of the GP AXI bus appears below. Of course this means that there is supporting software required to configure the modules. This software is included in the example under the software directory.

 

Here’s what’s connected to the M_AXI_GPIO port on the Zynq PS:

 

  • Port 0 – Connected to the Test Pattern Generator to enable the configuration of the test pattern being output
  • Port 1 – Connected to the VDMA 0 control and configuration input
  • Port 2 – Connected to the Video On Screen Display control
  • Port 3 – Connected to the On Semi PYTHON-1300 Color Image Sensor Camera Module
  • Port 4 - Connected to the Color Filter Array configuration
  • Port 5 – Connected to the VDMA 1 Control and configuration input
  • Port 6 – Connected to the On Semi Device SPI controller – This is needed as there is a non-power of two number of bits to be sent which prohibits the use of the on-device SPI.

 

The general-purpose AXI bus is used to configure the IP modules within the video stream. However, if we want to use capabilities provided within the PS half of the Zynq SoC, for instance to send the image data out over Ethernet, the image needs to be stored in an accessible location. This is normally the DDR memory. The image being stored is initially in the Zynq SoC’s on-chip memory so we use DMA to move the image from on-chip to DDR memory. DMA allows us to transfer large data blocks without the need for the processor to be heavily involved after the initial set up.

 

The demo design is configured to use Video Direct Memory Access (VDMA) IP to move image data from the Zynq PL (Programmable Logic) to the DDR memory if so configured. Once we have located a memory buffer area within the DDR memory, we can then use Zynq PS DMA to move data to this buffer or, if necessary, to perform some further algorithmic processing. This ability will be very important when we look more closely at the use of SDSoC for image processing.

 

Use of the DMA from the Zynq PL requires us to use the High Performance AXI port, which configures the Zynq PL as the AXI master and the Zynq PS as the AXI slave. As such, the VDMA module must be capable of both receiving and transmitting the video stream and reading and writing to a memory-mapped peripheral as shown in the diagram below:

 

 

 Image3.jpg

 

Green = AXI Streaming, Yellow = Memory Mapped AXI, Blue = AXI Lite, Orange = PS / DDR link

 

 

This example contains everything we need to do to get started with adding our own image-processing functionality. Before we do this though, I want to explore the VDMA in more detail as it will prove to be one of the key components in correctly using the Zynq to its maximum abilities for image processing.

 

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

 MicroZed Chronicles hardcopy.jpg

 

 

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

 MicroZed Chronicles Second Year.jpg

 

 

 

You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.