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Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD

by Xilinx Employee on ‎12-03-2014 07:07 AM (37,357 Views)

By Adam Taylor

 

Having looked at how we can update a running PicoBlaze program in previous blogs, we can now look at a complete application. A highly relevant application is driving a CCD (charge-coupled device) because there is often a need to modify the interface timing to fine tune the CCD drive waveforms to achieve optimal CCD performance.

 

The Zynq SoC is ideally suited for this application because the PS (Processor System) side of the device provides several methods of communicating with the external world for control and image output. The Zynq PL (Programmable Logic) side provides the FPGA fabric needed to generate timing-accurate CCD waveforms under the control of the Zynq PS so one might say this is a very traditional application for a system on chip.

 

CCD’s normally require much higher drive voltages than can be generated by an FPGA. Depending on the process technology used, a CCD can require drive voltages between 6 and 40V. However, the FPGA-generated waveforms can be level shifted from digital voltage levels using additional analog components such as operational amplifiers, so this is not much of a problem.

 

Driving a CCD requires the application of appropriate waveforms to the CCD’s image phase clocks and register clocks. The image clocks move the image one row (or section) at a time into the output registers and the image is then clocked out from the analog output registers under control of the register clocks. Often, CCDs have multiple regions and outputs allowing for a number of different waveform clocking regimes. You can use these features to increase CCD readout speed or to increase the reliability of a system should an output amplifier fail in very extreme cases.

 

Here’s an example of image clock and register clock waveforms for an e2v CCD230:

 

 

Image1.jpg

 

 

Image Clock Example for an e2v CCD230

(Registers Clocks at default levels during image clock active period)

 

 

Once an image section has been shifted into the analog output register, the register clocks are then used to clock the image out through the CCD’s output amplifiers. These amplifiers convert the stored charge representing the captured image into a voltage. Although this process seems very simple, configuring the CCD clock waveforms to achieve the best resultant image and performance can be incredibility complicated. This is especially true for high-performance CCD imaging.

 

 

 

Image2.jpg

 

 

CCD Register Clocks & Output Waveform for an e2v CCD230

 

Depending upon the number of image sections (see below) and read out amplifiers (there may be four to eight) within the CCD, it is possible to read out the image using waveforms generated by one or more PicoBlaze processors. It’s the PicoBlaze processor’s deterministic nature that makes this software-driven approach possible. Each PicoBlaze processor has eight outputs, which makes it possible to use PicoBlaze processors to generate image clocks, register clocks, or both types of clocks for simple CCD systems.

 

The number of PicoBlaze instantiations required to generate CCD waveforms in a system depends upon the number of CCD image sections and how the system designer wishes to partition the problem. The CCD will have multiple image clocks and register clocks (if there are multiple sections) and these can be commoned together and driven by a single PicoBlaze processor. Image clocks and register clocks can also be driven independently by their own PicoBlaze instantiation to obtain full CCD functionality.

 

The following illustration shows four different output modes and register-clocking schemes possible using the same CCD:

 

 Image3.jpg

 

Frame Readout Modes for an e2v CCD230

 

 

We can also use the PicoBlaze to configure any DAC / ADC in the circuit using a SPI or I2C interface. These devices, especially ADCs, are used to capture and digitize the CCD’s analog output waveform.

 

Once we have completed the initial waveform-generation program to drive the CCD, we may need to modify the waveform timing thus tuning the parameters to achieve more optimal CCD performance. This is where the ability of the Zynq PS to update the PicoBlaze waveform-generation programs during run time is key.

 

Over the next few blogs, we are going to create two PicoBlaze programs that we can use to drive a CCD. We’ll be using existing hardware that we developed in previous MicroZed Chronicles posts. Then we’ll look at how we can modify these programs during run time by developing an application for the Zynq SoC’s PS side to support this. The programmable flexibility we get from using PicoBlaze processors in the Zynq PL also means that we can clock the CCD using a number of different clocking schemes and change these schemes on the fly should it be required. Finally, the Zynq SoC’s PS will do more of the external communications and will send the received image externally over Ethernet, USB, or even write the images to SD cards.

 

For an introduction to CCDs and more information on clocking them, see Chris McFee’s online explanation here.

 

 

 

Please see the previous entries in this MicroZed series by Adam Taylor:

 

Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4

 

Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3

 

Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

 

Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze

 

Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

 

Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!

 

Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP

 

Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)

 

Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications

 

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

 

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

 

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

 

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts 

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

 

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

 

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

 

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

 

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

 

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

 

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

 

 Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

 

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

 

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28  

 

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

 

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

 

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

 

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

 

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

 

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

 

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

 

 

 

Comments
by Visitor dchallis
on ‎12-12-2014 12:59 PM

The waveform images will not load.

by Xilinx Employee
on ‎12-12-2014 01:12 PM

dchallis: If you mean the waveform images in the blog itself, they load properly on my system using both Firefox and IE. They also load properly on my mobile phone using Chrome. All of the images are JPEGs.

 

--Steve

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.