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Adam Taylor’s MicroZed Chronicles, Part 74: Physical Constraints

by Xilinx Employee ‎03-27-2015 11:51 AM - edited ‎03-27-2015 11:55 AM (13,843 Views)

 

By Adam Taylor

 

Having looked at timing-related constraints, we would be remiss if we did not consider the physical constraints that we can apply to our design. The most commonly used physical constraints an engineer uses is the placement of I/O pins and the definition of parameters associated with each I/O pin (standard, drive strength, etc.). However there are other types of physical constraints:

 

  • Placement Constraints – define cell location
  • Routing Constraints – define signal routing
  • I/O Constraints – define I/O location and I/O parameters
  • Configuration Constraints – define configuration methods

 

As always, there are a few constraints that sit outside these groups. Vivado has three and they are predominantly used on the Netlist:

 

  • DONT_TOUCH – used to prevent optimization. Can be of great use when implementing safety-critical and high-reliability systems.
  • MARK_DEBUG – used to preserve an RTL net so it can be used for debugging later.
  • CLOCK_DEDICATED_ROUTE – specifies a route for clock routing.

 

As mentioned above the most commonly used constraints relate to I/O placement and configuration. Just as important, these selections can have an impact upon the larger system and hardware. As a whole, they seem like a sensible place to start.

 

The placement of I/O on a FPGA uses both placement constraints to locate the physical pin and I/O constraints to configure that I/O’s properties (e.g. I/O Standard, Slew Rate etc.).

Modern FPGA’s support a number of different single-ended and differential I/O standards. These are defined via I/O constraints. However, the engineer must take care to ensure they are following I/O-banking rules, which depend upon the final pin placement.

 

But what are I/O Banking rules? Each of the user I/Os within a FPGA is grouped together into a number of banks consisting of a number of I/O pins. These banks have independent voltage supplies, adjustable at the bank level, that support a wide range of I/O standards.

 

On the Zynq SoC and other Xilinx 7 series devices, I/O banks are further classified into belonging to one of two overall groups, which further constrains their performance and requires that the engineer use the correct class for the correct interface. The first I/O bank classification is high-performance (HP), optimized for higher data rates. I/O pins in the high-performance bank class use lower operating voltages and do not support LVCMOS 3v3 and 2v5 I/O voltage levels. The High Range (HR) bank class is optimized to support I/O standards with wider voltage swings that are not supported by HP I/O banks. HR I/O banks support traditional 3v3 and 2v5 interfacing. The illustration below shows you the HR and HP I/O banks available in a Xilinx Kintex XC7K325T FPGA.

 

 

Image1.jpg

 

 

7 Series FPGA XC7K325T HR and HP I/O Banks

 

 

I/O banking rules for the HP and HR banks are defined in the table 1-55 of UG471. It is well worth your time to understand these rules from the earliest stages of development. Vivado provides the ability to create an I/O planning project to aid in this:

 

 

Image2.jpg

 

 

 

Image3.jpg

 

 

Once we have determined which I/O banks we will use for which signals, we still have the ability to change the signal drive strength and slew rate. These parameters will be of great interest to your hardware design team to optimize signal integrity on your board. These selections will also affect the timing of the board design.

 

Signal-integrity (SI) tools require an IBIS model of the I/O pin and we can extract an IBIS model of our design from Vivado when we have the implemented design open using the File->Export->Export IBIS model option. This file can then be used to close the system level SI issues and timing analysis of the final PCB layout.

 

 

Image4.jpg

 

 

Once the design team is happy with the SI performance and timing of the system as a whole, we will end up with a number of constraints like the ones shown below for the I/Os used in the design:

 

  • set_property PACKAGE_PIN G17 [get_ports {dout}]
  • set_property IOSTANDARD LVCMOS33 [get_ports {dout}]
  • set_property SLEW SLOW [get_ports {dout}]
  • set_property DRIVE 4 [get_ports {dout}]

 

We can also use the digitally-controlled impedance available with the HP I/O banks to properly terminate the I/Os and increase the SI of the system without the need for external termination schemes.

 

We must also consider the effects of the I/O if there is no signal driving it. For instance, if the I/O pin is connected to an external connector, we can use the I/O constraints to implement a pull up or down resistor to prevent the FPGA input signal from floating. Floating inputs can cause persistent and intermittent system issues.

 

Of course we can also use Physical Constraints to improve design timing by implementing the final output flip flop within the I/O block itself. Doing so reduces the clock-to-output timing. We can do the same thing on input signals as well, which allows the design to meet the pin-to-pin set-up and hold timing requirements.

 

In the next blog we will look at how we can use the placement and routing constraints upon our logic design within the FPGA.

 

 

Please see the previous entries in this MicroZed Chronicles series by Adam Taylor:

 

Adam Taylor’s MicroZed Chronicles, Part 73: Working with other Zynq-Based Boards

 

Adam Taylor’s MicroZed Chronicles, Part 72: Multi-cycle Constraints

 

Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Clock Relationships and Avoiding Metastability

 

Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

 

Adam Taylor’s MicroZed Chronicles Part 69: Zynq SoC Constraints Overview

 

Adam Taylor’s MicroZed Chronicles Part 68: AXI DMA Part 3, the Software

 

Adam Taylor’s MicroZed Chronicles Part 67: AXI DMA II

 

Adam Taylor’s MicroZed Chronicles Part 66: AXI DMA

 

Adam Taylor’s MicroZed Chronicles Part 65: Profiling Zynq Applications II

 

Adam Taylor’s MicroZed Chronicles Part 64: Profiling Zynq Applications

 

Adam Taylor’s MicroZed Chronicles Part 63: Debugging Zynq Applications

 

Adam Taylor’s MicroZed Chronicles Part 62: Answers to a question on the Zynq XADC

 

Adam Taylor’s MicroZed Chronicles Part 61: PicoBlaze Part Six

 

Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD

 

Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4

 

Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3

 

Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

 

Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze

 

Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

 

Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!

 

Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP

 

Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)

 

Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications

 

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

 

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

 

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

 

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts 

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

 

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

 

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

 

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

 

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

 

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

 

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

 

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

 

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

 

 Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

 

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

 

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28  

 

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

 

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

 

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

 

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

 

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

 

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

 

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.