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The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28

by Xilinx Employee ‎04-16-2014 10:49 AM - edited ‎04-16-2014 10:49 AM (27,574 Views)

In my last blog we had just arrived at the point where the benefit of using DMA (Direct Memory Access) had become obvious, although I previously alluded to the benefit of using DMA coupled with the AXI interfaces in Part 21 of this series.

 

Having reached this point, we’re left with the question mankind has long pondered: What exactly is DMA?

 

At its most basic level, DMA transfers data into or out of memory without processor intervention once the processor has set up the transfer. DMA can significantly increase system performance depending upon the approach taken.

 

Before we look at Zynq DMA in more detail, I would first like to explain a few generic principles of DMA controllers.

 

Typically DMA controllers operate in one of three modes:

 

  • Burst Mode - Transfers an entire data block in one continuous operation. In many applications, burst-mode transfers deny bus access to the processor while the DMA is taking place. This could be perfectly fine or it could be a very bad thing depending on the system.
  • Cycle Stealing – Interleaves individual DMA byte or word transfers with processor accesses to the system bus. This mode prevents processor starvation.
  • Transparent mode – The most efficient mode. Data is only transferred when the processor is performing tasks that don’t require access to the system bus.

 

One very useful feature of DMA Controllers is the ability to support scatter/gather operations. This feature enables multiple data sources to be transferred to a single destination address or allows a single source address to supply multiple output destinations (also called “buffers”).

 

The Zynq SoC’s ARM-based Processing System (PS) has a DMA Controller (DMAC) that’s connected to the Zynq’s AXI4 central interconnect and uses the AXI bus to perform transfers. The DMAC employs 64-bit AXI transfers between system memories and the Zynq’s Programmable Logic (PL). As shown below, the Zynq DMAC has eight channels which allow the DMAC to execute eight DMA threads concurrently with flow control achieved via the AXI interconnect.

 

 

 Figure 1.gif

 

 

While the Zynq DMAC allows bidirectional transfer between system memories and PL (including the Zynq peripherals in the PL), it does not support DMA for peripherals in the Zynq PS because these have no flow-control signals to support DMA operations. However, several of the IO peripherals in the Zynq SoC have their own DMA Controllers to support high data rate transfers to or from the IOP and system memory. These peripherals are:

 

  • GigE Controller
  • SDIO Controller
  • USB Controller
  • Device Configuration Controller

 

The Zynq SoC also provides support for secure register access if the device is utilizing the ARM TrustZone.

 

Xilinx rather helpfully provides a simple driver file (xdmaps.h) that we can use within the standalone BSP to configure and initiate DMA transfers. In my next blog we will look at how we can create a simple DMA transfer using this file.

 

 

 

Please see the previous entries in this MicroZed series by Adam Taylor:

 

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

 

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

 

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

 

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

 

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

 

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

 

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

 

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

 

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

 

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

 

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

 

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

 

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

 

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

 

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

 

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

 

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

 

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

 

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

 

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

 

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado

 

 

(Note: This 28th instalment of Adam Taylor’s MicroZed Chronicles is also the 300th Xcell Daily blog post. A hearty “Thank you” to Adam for helping us reach this milestone!)

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.