Thinking of switching to Xilinx? Read this

by Xilinx Employee on ‎10-02-2015 02:34 PM (572 Views)


I have had a hard and fast rule in the Xcell Daily blog. I focus the blog on what Xilinx, its partners, and its customers are doing and I don’t bother writing about the competition because I don’t think you’d find it very helpful coming from me. However, the fates have handed me an exception to this rule in the form of a new User Guide that’s potentially helpful to FPGA users. So if you don’t want to see me cross the line, please stop reading this blog entry now.





OK, now we’ve crossed the line, but just for a minute.


Xilinx has just published a new User Guide titled “UG1192: Xilinx Design Flow for Altera Users.” If you’re considering a switch to Xilinx for whatever reason, it discusses things you need to know like hardware-specific architectural differences including differences in I/O pins, transceivers, clocking, internal memory, DSP resources, and external memory interfaces. It also discusses similarities and differences in design tools and IP cores including some things that the Vivado Design Suite does not support and some things that Vivado supports that are not supported by competitive tools. It discusses how to convert your constraint files and it discusses significant differences in simulation capability (Vivado appears to have a big advantage here).


It’s likely that somewhere in this 61-page document, you will find something or maybe several somethings that you didn’t think about yet—if you’re considering switching to Xilinx All Programmable devices. If you are, you should definitely take a look at this user guide.






We now return to our regularly scheduled programming.



Some new dual-voltage 20nm Xilinx Virtex UltraScale devices appeared today on the Xilinx secret menu, aka the UltraScale Product Selection Guide. You can operate these -1H devices at 0.95V for low operating power or at 1V for more performance. Operated at 0.95V, these FPGAs give you the low operating power of -1 Virtex UltraScale FPGAs. Operate them at 1V and you get the equivalent of a -2 speed grade with just a 6.5% increase in operating power. Same device; extended temperature range (0-100°C); your choice.


Oh, and something magical happens to the GTH and GTY SerDes ports on these -1H devices. At 0.95V, the GTH and GTY max data rates are both 12.5Gbps—good enough for lots of things including 10Gbps Ethernet. Bump the supply voltage to 1V and the line rates jump to 16.3 and 25.7Gbps respectively.




The -1H speed grade applies to all 20nm Virtex UltraScale devices except for the XCVU440.


Want more info? Contact your friendly neighborhood Xilinx salesperson.



Yesterday, Xilinx announced first customer shipments of the 16nm Zynq UltraScale+ MPSoC and the blog covering that announcement showed the device running a “Hello World” program. (See “Lift-off! 16nm Zynq UltraScale+ MPSoC ships to customers. From tapeout to “Hello World” in 2.5 months.”) From that video, you can tell that the processors are running and that the device can at least drive a UART, but what about the high-speed SerDes transceivers? Those are pretty darn important too, aren’t they?


Glad you asked.





The new Avnet PicoZed SDR board implements a complete software-defined radio on an incredibly small, 100x62mm board by pairing a Xilinx Zynq Z7035 SoC with an Analog Devices AD9361 integrated RF Agile Transceiver—a very potent combination. The resulting SDR radio subsystem (actually, you could build entire SDR systems with just this board, RF amps, antennas, a power supply, and an enclosure) has a 70MHz to 6GHz RF operating range and can handle a 2x2 MIMO antenna array. You can program this board using a tailored version of the MathWorks Communications System Toolbox for MathWork’s MATLAB and Simulink design and simulation environments and the board is designed to be a SOM (system on module) that you can use as a production-ready, system-level RF component. Initial tests of this system implemented an entire LTE radio system that consumed less than 5W.


Here’s a photo of the board next to a US 25-cent coin for size comparison:



Avnet PicoZed SDR.jpg




Avnet PicoZed SDR SOM




You read that right. ARTY is the new $99 FPGA Dev Board/Eval Kit featuring a low-power Artix-7 A35T -1LI FPGA.




ARTY Board v2 White.jpg

 The ARTY Artix-7 FPGA Dev Board




(Note: Digilent calls ARTY a Dev Board while Xilinx and Avnet call it an Eval Kit. Same board, different name.)


The low-cost ARTY Artix-7 FPGA board has the following features:


  • Artix-7 A35T –L1 Low-Power FPGA
  • 256Mbytes of DDR3-1066 SDRAM (16-bit interface)
  • Arduino Shield Expansion Port
  • Four Digilent Pmod connectors
  • 10/100 Ethernet Port
  • Four user slide switches
  • Four pushbutton switches
  • Four monochrome LEDs
  • Four RGB LEDs



Here’s a block diagram of the board taken from the Avnet product data sheet:




ARTY Block Diagram.jpg



ARTY Artix-7 FPGA Dev Board Block Diagram



In addition to the board, you get a device-locked copy of Xilinx Vivado Design Edition, which includes a mixed-language simulator, a logic analyzer, a serial I/O analyzer, and debugging IP that are not included in the Vivado WebPACK Edition. You can also download additional design resources, example projects, and tutorials from an ARTY-specific portion of the Web site.


Normally, you need to fork over $2995 for a Vivado Design Edition license. A voucher code for your device-locked copy of the Xilinx Vivado Design Edition is included in the $99 price of the ARTY Dev Board/Eval Kit.




Here’s a short, 8-minute video with additional information on ARTY presented by my friend and fellow maker, Jim "Jimbo" Burnham:






If you’ve been waiting to jump from your present FPGA development software to Xilinx Vivado, this would be the time.


You should be able to order an ARTY board today from either Digilent or Avnet. Go for it!


The date September 30 has been circled in red for a few weeks here at Xilinx HQ. It’s the ahead-of-schedule date Xilinx planned to announce first customer shipments of the 16nm Zynq UltraScale+ MPSoC, which taped out last July. (See “We have Tapeout! Xilinx Zynq UltraScale+ MPSoC ready for TSMC’s 16FF+ process.”) Well, today is September 30 and Xilinx has announced first customer shipments of the Zynq UltraScale+ MPSoC.


I love it when a plan comes together—even better when faster than planned.


Just a quick reminder:


The Xilinx Zynq UltraScale+ MPSoC simply has a lot more of everything including:


  • Quad-core, 64/32-bit ARM Cortex-A53 processor for immense application-processing power
  • Dual-core, 32-bit ARM Cortex-R5 processor for real-time and safety-critical software execution
  • ARM Mali-400 MP GPU for implementing high-performance graphics, offloading these tasks from the on-chip ARM Cortex-A53 CPUs and the ARM Cortex-R5 real-time processors
  • A hardened H.265/264 Video Codec Unit that provides native UltraHD compression
  • Dedicated Security Processing Unit with multiple military-class security protocols to prevent any conceivable unauthorized access
  • Hardened, integrated SDRAM memory controller supporting DDR4, LPDDR4, DDR3, DDR3L, and LPDDR3 memory devices
  • Large arrays of Xilinx UltraScale+ programmable logic including the new, larger embedded UltraRAM blocks; a large number of UltraScale DSP48E2 slices; and hardened, integrated PCIe Gen2/Gen3/Gen4 and 100G Ethernet blocks
  • Xilinx programmable I/O that can handle anything from simple logic pins to high-speed PCIe and 100G+ Ethernet serial protocols



Now, it’s one thing to simply say that we’ve shipped the product. Showing you a photo of a live Zynq UltraScale+ MPSoC is another thing entirely, so here you go:




Zynq UltraScale MPSoC on a Characterization Board.jpg


16nm Xilinx Zynq UltraScale+ MPSoC




Finisar demos 400G SR16 optical link at ECOC 2015—driven by a “400GE Xilinx FPGA”

by Xilinx Employee ‎09-29-2015 04:52 PM - edited ‎09-29-2015 04:57 PM (392 Views)

This week, Finisar is demonstrating error-free operation a 400GE CFP8 optical module at the ECOC 2015 conference currently underway in Valencia, Spain. The live demo uses “four Finisar 100GE CFP4 SR4 modules driven by a 400GE Xilinx FPGA.” The company is also displaying a 400GE CFP8 module.


See the Finisar press release here.

The Zynq-based Skreens Nexus is a real-time HDMI video switcher/combiner that accepts two or four HDMI video sources and outputs a user-defined, merged video stream to an HDMI display—for $400 or less. This Kickstarter project is aimed at multiple consumer-oriented markets—especially gamers and sports enthusiast who want to play or watch a live game in one window while watching social-media side channels like Twitter, Skype, or other chat windows and perhaps while being able to watch additional live television content at the same time.


Minutes ago, the Kickstarter campaign went north of $200K (800% funded) when the 560th backer signed up.


There are still 33 days remaining in the Kickstarter campaign. Don’t your kids need one? Better yet, don’t you need one?



Skreens NexusFour.jpg



Skreens NexusFour HDMI Video Switcher/Combiner



For more information about the Skreens Nexus, see:


Zynq-based, $179 Skreens Nexus on Kickstarter allows you to safely cross the (HDMI video) streams




45-minute video provides in-depth details regarding the Zynq-based Skreens HDMI streaming video combiner/switcher

We’ve all seen video-centric control and decision-support rooms so many times—at MI6 HQ in James Bond movies, in broadcasts of space launches at NASA and ESA, and even front and center at CERN supporting the Higgs boson researchers—that they sort of blend into our mental scenery. But it takes a lot of video wizardry to take any arbitrary set of video streams and place them cleanly, clearly, and intelligently on a wall mosaic built from multiple video displays and projectors. RGB Spectrum in Alameda, California has been doing just that for nearly 30 years. Earlier this year, the company introduced its next-generation MediaWall V UHD Display Processor, the world’s first video-wall display processor designed to reach new markets driven by 4K-video by handling true, any-to-any UHD video from source to display and they’re using three generations of Xilinx FPGAs to do it.



RGB Spectrum MediaWall V Display Processors.jpg 


RGB Spectrum MediaWall V Display Processors, 6RU and 3RU Configurations



The MediaWall V Display Processor’s architecture combines real-time, hardware-based video processing with a separate processor to run applications. The result is a 4K video wall processor with enough power and versatility to drive both HD and UHD video wall systems. In its maximum Model 550 (6RU) configuration, the MediaWall V processor accepts as many as 36 UHD video or graphic direct inputs and outputs video to as many as 28 display devices. It processes a full range of video resolutions from 4K (4096 x 2160) and UHD (3840 x 2160) to 2K (2048 x 1152/1080) and HD (1920 x 1080). The display processor can scale each input stream individually for output to a UHD video wall or for display on standard video walls. An optional Application Processor decodes IP camera and other H.264 streams. Built-in HDCP capability allows the display of protected content.




Need several million ASIC-gate equivalents for your FPGA prototyping? One way to do that is to use the world’s largest FPGA, the Xilinx Virtex UltraScale VU440—with 4.433M logic cells (equivalent to roughly 44M ASIC gates)—the way that S2C did with its recent introduction of the Single VU440 Prodigy Logic Module. (See “Phenomenal Cosmic Prototyping Power, Itty Bitty Package: The new S2C Single VU440 Prodigy Logic Module.”) Another approach, also taken by S2C on its brand new Quad Kintex UltraScale Prodigy FPGA Prototyping Logic Module: combine four Xilinx Kintex UltraScale KU115 FPGAs on one board with an aggregate capacity of 4.644M logic cells, equivalent to roughly 46.4M ASIC gates. But ASIC prototyping logic gates are not really the story here. This story’s about DSP.


A lot of DSP.


After all, we’re talking about the Xilinx Kintex UltraScale KU115 FPGA.



S2C Quad Kintex UltraScale Prodigy FPGA Prototyping Logic Module.jpg




S2C Quad Kintex UltraScale Prodigy FPGA Prototyping Logic Module




Here’s a block diagram of this new board:



S2C Quad Kintex UltraScale Prodigy FPGA Prototyping Logic Module.jpg



S2C Quad Kintex UltraScale Prodigy FPGA Prototyping Logic Module Block Diagram




And here’s a spec comparison of S2C’s two UltraScale-based FPGA Prodigy Prototyping Modules:



Prodigy Module

Single VU440 Prodigy Logic Module

Quad Kintex UltraScale Prodigy Logic Module

Logic Cells



Block RAM (Mbits)



DSP Slices








A few things jump out at you from this table. Four Kintex UltraScale KU115 FPGAs give you more resources than one Xilinx Virtex UltraScale VU440 FPGA. You get a lot more block RAM and nearly 10x the number of DSP slices with the Quad Kintex UltraScale prototyping board. You don’t get any more I/Os however because that’s a board/connector limitation. Both boards are part of the company’s Prodigy Complete Prototyping Platform.


Put a few of these bad boys in your S2C Cloud Cube if your design needs phenomenal, cosmic DSP capabilities.



Fabless, the book—now available free if you know how

by Xilinx Employee on ‎09-28-2015 01:36 PM (822 Views)

Early last year, Daniel Nenni and Paul McLellan wrote the book about the fabless semiconductor industry. (See “Absolutely Fabless: SemiWiki’s new book on the Fabless Semiconductor industry launches.”) I contributed a chapter to this book about the founding of Xilinx—the industry’s first fabless semiconductor vendor, founded in 1984. The first Xilinx chips rolled out of the Seiko fab almost exactly 30 years ago in 1985. Here’s a close-up photo of an ES001 engineering sample of the world’s first FPGA, Xilinx’s first device, the XC2064:



XC2064 Engineering Sample circa 1985.jpg



Xilinx XC2064 Engineering Sample—the world’s first FPGA. Photo Credit: Anthony Collins



(For more information about the XC2064, see “The Xilinx XC2064: the ur-FPGA — a 48-pin DIP snatched from the mists of time for a 30th power-on anniversary.”)



Although I’ve previously posted a PDF of the Xilinx chapter from the Fabless book, you can now download the entire book as a PDF simply by registering in the SemiWiki web site. It’s well worth the read.



Click here and register for your free PDF of the “Fabless” book.



By Adam Taylor



Well this was supposed to be the easy one. I should have known better.


Sitting down to create the FreeRTOS project I read the SDSoC User Guide 1027, which states that FreeRTOS is supported for the ZC702 and ZC706 boards only. However, if you are a regular follower of this blog then you will know we have previously run FreeRTOS on the MicroZed.


Indeed while this blog is going to show you how the AES encryption behaves when running FreeRTOS, it is also going to show you how to get FreeRTOS running on the MicroZed using SDSoC.


The first thing we need to do is create an SDSoC Project targeting the MicroZed and using the FreeRTOS operating system:







This will create a blank project, within which we can create our application running as a FreeRTOS task. The libraries for FreeRTOS are included under the arm-xilinx-eabi, mapped when you create the project.








However before we can build the project we must also update some files contained within the Xilinx SDSoC Platforms MicroZed directory to ensure that SDSoC can build the application for the MicroZed. We must do the following:



  1. Update the microzed_sw.pfm file to include information on FreeRTOS below:






  1. Within the same file (microzed_sw.pfm), include the location of the bif file for creating the FreeRTOS boot files.







  1. Within the platforms directory, copy the FreeRTOS directory to the microzed directory from the ZC702 directory—this contains the linker script for the build with the location of the FreeRTOS vectors.



  1. Within the platforms/microzed/boot directory, copy the standalone.bif, paste and rename as freertos.bif



With the above stages completed, we should be able to build our application once we have written it.


FreeRTOS employs tasks so we will be writing the example code as one task and then starting the scheduler. To do so, we must modify the previously software written for the AES example slightly so that it can run as a task. We must also run a special function that configures the hardware correctly for use with SDSoC and FreeRTOS. This function updates the interrupt vector table for use with FreeRTOS. Failure to include this function will result in the task being created but the scheduler not starting correctly.


With this all created, I converted the main() program from the previous example and renamed it as a function called protect(). This function can be called as a task by FreeRTOS.


I created a task and started the scheduler within the new main function. The task executes the AES encryption function. To prevent the task from running continually, I pause the scheduler after it has executed once.


Once all this has been completed, I built the application and ran it on the MicroZed to again establish a performance baseline for comparison against the accelerated performance and against the Linux and Standalone examples.


The performance from software-only PS execution on the Zynq SoC is very similar to that from the Linux:








I achieved the following result when I accelerated the AES code with the same settings as before:






This result is very similar to the bare-metal implementation performance we’ve seen previously, which is not so surprising because FreeRTOS is a much simpler operating system than Linux. With only one task running, results should be very similar to bare-metal operation.


These performance numbers allow me to create a table of the three operating systems and the performance in the Zynq SoC’s PS and PL:



Operating System

PS Only

PS with PL acceleration
















Next week I am going to start looking at how we could add another different operating system to SDSoC.


The files as always are on the github repository.



If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.




  • First Year E Book here
  • First Year Hardback here.



 MicroZed Chronicles hardcopy.jpg




  • Second Year E Book here
  • Second Year Hardback here



 MicroZed Chronicles Second Year.jpg




You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.




Want to learn how to use the recently announced Synopsys HAPS-80 FPGA-based prototyping systems in your work? This free September 30 Webinar is for you. Senior Product Marketing Manager Neil Songcuan will discuss automated ways of partitioning your design using the Synopsys ProtoCompiler to run on the modular HAPS-80 system, which can be configured for prototyping capacities to 1.6 billion ASIC gates. (The HAPS-80 system is based on the Xilinx Virtex UltraScale VU440 FPGA.)


Register here.


For more information on the Synopsys HAPS-80 system, see “Synopsys’ new HAPS-80 FPGA-Based Prototyping System harnesses world’s largest FPGA: Xilinx Virtex UltraScale VU440.”

Zynq-based, 40-pin DIP emulation of 8-core Parallax Propeller enters Hackaday semifinals

by Xilinx Employee ‎09-24-2015 09:34 AM - edited ‎09-25-2015 03:38 PM (1,348 Views)

HAckaday Prize Logo.jpgParallax has served the maker community for more than two decades starting with the extremely popular BASIC Stamp microcontroller (based on a Microchip PIC) and associated training. The BASIC Stamp is a simple microcontroller. The latest Parallax foray into embedded control is the Propeller P8x32A, a custom multicore chip with eight 32-bit cores, its own programming language dubbed Spin, and a GUI called the Propeller Tool.


The Parallax Propeller first appeared in 2006 and Parallax released the Verilog code and top-level HDL files for the Propeller 8x32A in 2014. Antti Lukats, R&D manager at Xilinx Certified Alliance member Trenz Electronic, thought it would be a cool idea to take that Verilog code and add the eight Propeller 32-bit processor cores to the Xilinx Zynq SoC’s existing dual-core ARM Cortex-A9 MPCore processor using the Zynq SoC’s programmable logic fabric. Lukats used the smallest member of the Zynq SoC family, the Z-7010, to implement the Parallax Propeller.


The result: a Soft-Propeller Zynq FPGA Board—a 40-pin DIP module based on a Xilinx Zynq Z-7010 SoC that’s now a semifinalist in the 2015 Hackaday Prize competition, which received more than 900 entries this year.


The grand prize in this competition is a trip into space. Hence the space-helmeted skull in the prize logo.



Soft-Propeller Zynq FPGA Board.jpg


Soft-Propeller Zynq FPGA Board based on a Xilinx Zynq Z-7010 SoC



Just minutes ago, the Skreens Kickstarter campaign funding level crossed the 400% funding threshold.


Looks like we have a winner!


Hard to say what the final Kickstarter pledge tally will be but it’s going to be way, way beyond the original $25K goal. Zynq-based Skreens is a real-time HDMI video combiner that accepts two or four HDMI video sources and outputs a user-defined, merged video stream to an HDMI display. It’s aimed at multiple consumer-oriented markets—especially gamers and sports enthusiast who want to play or watch a live game in one window while watching social-media side channels like Twitter, Skype, or other chat windows and perhaps while being able to watch additional live television content at the same time. However, Skreens Nexus HDMI switcher can do a lot of what’s done in a $6K broadcast video switcher—but for $400 or less.



Skreens NexusFour.jpg



Skreens NexusFour HDMI Video Combiner/Switcher


How to maximize performance per Watt using Xilinx UltraScale All Programmable devices

by Xilinx Employee ‎09-23-2015 10:59 AM - edited ‎09-23-2015 11:05 AM (574 Views)

Trying to push the performance envelope but constrained by cast-in-concrete power budgets? You can increase performance while avoiding runaway power consumption and the accompanying ills (bigger power supplies, heat sinks, cooling fans, and energy costs) by using hardware, software, and I/O programmability in conjunction with more advanced FPGAs and MPSoCs based on the Xilinx UltraScale architecture. The following 23-minute EE Journal Chalk Talk video discusses these issues and how Xilinx is addressing these design needs with power-saving architectural and I/O innovations and FinFET-based IC process technology:




As a follow-on to the introduction of the Synopsys HAPS-80 FPGA-based prototyping system family (see “Synopsys’ new HAPS-80 FPGA-Based Prototyping System harnesses world’s largest FPGA: Xilinx Virtex UltraScale VU440”), long-time EDA blogger Peggy Aycinena recently published a related telephone interview with Johannes Stahl, Synopsys Director of Product Marketing for Prototyping. Peggy asked Stahl if he could have foreseen, even 15 years ago, the speed and capacity that would be available in FPGA-based prototyping systems today. Stahl’s reply:


“The answer is no, but there has been a very important driving force for all of this progress – the dream of a fully implemented software prototyping system that could also meet the needs of customers who could not afford debug problems in their designs. We believe that with our new HAPS-80 release, we’re making both of these dreams come true. Now, creating a physical implementation of a design prototype has been reduced from something like a wrestling match to something more like a ping-pong match.”


Zynq-based, $179 Skreens Nexus on Kickstarter allows you to safely cross the (HDMI video) streams

by Xilinx Employee ‎09-22-2015 04:52 PM - edited ‎09-22-2015 04:56 PM (1,181 Views)

From the movie “Ghostbusters”:


Egon Spengler: There's something very important I forgot to tell you.


Peter Venkman: What?


Spengler: Don't cross the streams.


Venkman: Why?


Spengler: It would be bad.


Venkman: I'm fuzzy on the whole good/bad thing. What do you mean, "bad"?


Spengler: Try to imagine all life as you know it stopping instantaneously and every molecule in your body exploding at the speed of light.


Ray Stantz: Total protonic reversal!


Venkman: Right. That's bad. Okay. All right. Important safety tip. Thanks, Egon.



The Zynq-based Skreens Nexus allows you to merge multiple video streams (including the “Ghostbusters” movie) and display them on one HDMI device under the control of a built-in browser or your iOS or Android phone. Combine the video streams from multiple movies, TV channels, satellite boxes, computers, game consoles, cameras and camcorders, GoPro and other Xtreme video cameras, whatever, and present them on one big, tiled display. This Kickstarter project is so hot that it’s already 200% funded one day into the Kickstarter campaign. Only 39 days to go. The first 250 backers can get a Skreens NexusTwo with two HDMI inputs for $179. Another 250 backers can get a Skreens NexusFour with four HDMI inputs for $325. After that, the prices rise to $199 and $370 respectively. You’ll need the higher-priced PRO versions to get additional features such as universal remote in the Skreens iOS or Android controller, streaming audio over Wifi/BT, and a developer API.


Here’s the Kickstarter video:






The rugged, metal-encased Miracle2 Micro Rapid Controller and Logging Environment from Alma Automotive is designed to handle heavy-duty processing in automotive applications ranging from combustion analysis, data logging, and hardware-in-the-loop (HIL) testing to complex electronic control. Miracle2 relies on the Zynq-based Single-Board RIO (SBRIO) SOM from National Instruments (NI) to perform the processing and control tasks. (For more information on the NI Zynq-based SOM, see “NI’s new Zynq-in-a-box SOM targets embedded development with dual-core ARM Cortex-A9.”)



 Alma Automotive Zynq-Based Miracle2.jpg



Alma Automotive’s Zynq-based Miracle2 Micro Rapid Controller and Logging Environment

Photo Credit: Dan Isaacs



One key advantage to using the NI SBRIO SOM is that it’s programmed using NI’s LabVIEW system-design software, which permits rapid prototyping of very complex control and data-acquisition systems. The integrated Xilinx Zynq Z7020 SoC allows the module to provide real-time hardware response to complex stimulus—essential in automotive environments including engine and gearbox control. (See NI’s “Top 10 Reasons to Use NI LabVIEW for Designing Embedded Systems” for a lot more information.)


One example application dubbed OBI-M2 is a combustion-analysis and data-logging system for internal-combustion engines with as many as 12 cylinders. OBI-M2 can be connected to standard crankshaft position sensors—no crank-angle adapter needed. An optional Champion integrated charge amplifier connects to the Miracle2 for handling piezoelectric pressure sensors. When connected to the application engineer’s laptop, the OBI-M2 user interface can stream real-time cylinder-pressure measurements over Ethernet for post-processing view and analysis.


Alma Automotive’s Web site discusses several additional LabVIEW-based automotive application case studies including:




Many restaurants have “secret menus.” (See In-n-Out burger’s secret menu here.) A new 20nm Xilinx Kintex UltraScale FPGA just appeared in the Xilinx UltraScale Product Table. It’s called the Kintex UltraScale KU025 and even though it’s the smallest Kintex UltraScale device yet—it’s still “huuuuuuge!” Here’s a few of the Kintex UltraScale KU025 FPGA’s specs:



Logic Cells


Block RAM


DSP Slices


PCIe Gen1/2/3 hardened embedded core


16.3Gbps Transceivers


Max single-ended HP I/Os


Max Single-ended HR I/Os


Max differential HP I/O pairs


Max differential HR I/O pairs




Selected Kintex UltraScale KU025 Specifications




Compare this smallest Kintex UltraScale device with the Kintex-7 family and you’ll see that it has more logic cells than the smallest Kintex-7 device, more block RAM than the two smallest Kintex-7 devices, more DSP slices than the smallest three Kintex-7 devices, more serial transceivers than the two smallest Kintex-7 devices, and faster serial transceivers than any Kintex-7 device.


Worth a look.






Two weeks ago, I wrote about the $349, Crowd-Sourced, FPGA-based Numato Opsis Video Dev Platform on the CrowdSupply crowdsourcing site (see “Cool, $349, Open-Source, FPGA-based Video Dev Platform supports HDMI, VideoPort, USB, Ethernet”) and stated “…based on my experience with Xcell Daily’s readers, I expect the project will be fully funded by the end of this week.” Sure enough, this very cool video project based on a Xilinx Spartan-6 LX45T FPGA is 120% funded with 35 days left in the funding period. So if you need HDMI in/out, DisplayPort in/out, USB, and Gigabit Ethernet ports for your next project—not to mention a pretty darn good, video-capable FPGA—you still have five weeks to pledge your $349 for one of these bad boys.




Numato Opsis Spartan-6 Video Dev Board.jpg




A: HDMI Out 1

B: HDMI Out 2

C: HDMI In 1

D: HDMI In 2

E: DisplayPort Out

F: DisplayPort In

G: USB 2.0 Device / JTAG Programmer / UART Adapter

H: Expansion Port (TOFE, not PCI-Express compatible)

I: microSD (underside of board)

J: USB 2.0 OTG

K: Gigabit Ethernet



Thinking high-speed optical interconnect (SFP+, QSFP28, CFP4, etc.)? Watch this 4-minute video

by Xilinx Employee ‎09-21-2015 10:22 AM - edited ‎09-21-2015 10:44 AM (458 Views)

Here’s a concise, 4-minute video that walks you through the availability of high-speed optical interconnect interfaces on three Xilinx Virtex UltraScale and Kintex UltraScale FPGA Eval and Dev Kits:





This video made by the ever-entertaining Martin Gilpatric, Xilinx Transceiver Technical Marketing Manager, gives you a good, quick overview of high-speed optical interfacing options available on the three Xilinx UltraScale FPGA boards listed above:






For more information on high-speed optical interfacing using Xilinx UltraScale FPGAs, click here.






By Adam Taylor



We’re starting the third year of this series. Over the next few blogs, I plant to redo the same AES example we’ve been exploring with Linux using both Free RTOS and the bare-metal SDSoC option. This will ensure that no matter which of the operating systems we use for our application, we will have the topic covered.


As engineers, it is our responsibility to select the correct operating system for the application when we define a system’s architecture. Each project will have different requirements including response times (is an RTOS required?), networking support, file systems etc. We must also remember that for many of these applications, we want to be first to market—so heritage and experience also count.


I am going to start by looking at bare-metal systems. As such, we first need to create a new SDSoC project. We select the standalone option for the OS as shown below:







Look what the TARDIS just brought: An engineering sample of the World’s First FPGA from 1985

by Xilinx Employee ‎09-18-2015 11:07 AM - edited ‎09-18-2015 11:39 AM (656 Views)

I thought buying a 1988 copy of a Xilinx XC2064 FPGA from eBay was special but Anthony Collins at Xilinx in Dublin has got the “real” ur-FPGA: an ES001 engineering sample of an XC2064 from 1985, packaged in a 68-lead PLCC. Here’s the photo Anthony sent to me:



XC2064 Engineering Sample ES001.jpg 



Looks like the engineering sample, the chip on the right, came first in the thirty-second week of 1985. No need to identify which device it was because there was only one at the time. The chip on the left is stamped on top with the familiar Xilinx logo, the production part number, and the date code (8543).


Anthony is a Senior Staff Technical Marketing Engineer and he was in San Jose many years ago when he found engineering samples of the world’s first FPGA. He was cleaning up a lab bench in preparation for work on some 90nm FPGA first silicon. I wasn’t working for Xilinx at the time, but according to the “big wall o’ corporate history” we keep here at Xilinx HQ in San Jose, that first silicon could have been a Spartan-3 FPGA design, the world’s first 90nm FPGA, introduced in 2003. (For the Spartan-3 introduction stories, see this Summer 2003 issue of Xcell Journal.) However, Anthony says it was actually Virtex-4 FPGAs, introduced a couple of years later. Among other things, Virtex-4 FPGAs introduced the world to XtremeDSP (DSP48) slices. (See this special issue of Xcell Journal for more information on the Virtex-4 device family introduced in 2005.)


Note: For more information about the world’s first FPGA, see “The Xilinx XC2064: the ur-FPGA — a 48-pin DIP snatched from the mists of time for a 30th power-on anniversary.”

Avnet has just announced the ONIX-VU440 Development Board and Prototyping Platform, based on world’s largest shipping FPGA—the 20nm Xilinx Virtex UltraScale XCVU440. The ONIX-VU440 PCIe card supports three operating modes:


  • Desktop standalone mode
  • PCIe plug-in card mode
  • Mezzanine module mode, with two interconnected ONIX boards in a standard 3U rack



Avnet ONIX-VU440 Dev Board and Proto Platform.jpg



Avnet ONIX-VU440 Development Board and Prototyping Platform



The board accepts one 1-16Gbyte DDR4 SDRAM SODIMM for expansion memory, in case the XCVU440 FPGA’s 88.6Mbits of on-chip block RAM aren’t sufficient for your application.

The just-announced Synopsys HAPS-80 modular, FPGA-based prototyping system can scale from 26 million to more than 1.6 billion ASIC gates—using from one to 64 Xilinx Virtex UltraScale FPGAs—to accommodate any sort of design from individual IP blocks, to processor sub-systems, to entire SoCs.



Synopsys HAPS-80.jpg



Synopsys HAPS-80 FPGA-Based Prototyping System





by Xilinx Employee ‎09-17-2015 10:38 AM - edited ‎09-17-2015 11:13 AM (1,035 Views)

“San Jose, Calif., Sept. 17, 1987 -- Xilinx (tm) Inc. today introduced the world's most powerful user-programmable gate array -- incorporating an enhanced second-generation architecture to extend the performance and design capabilities of the company's patented Logic Cell (tm) Array family.


The new XC3020 includes the equivalent of 1800-2400 two-input NAND gates, a new 1.2 micron CMOS process, and a 40 MHZ system clock rate, making it the industry's fastest CMOS programmable logic product. This gives designers the performance and density necessary to integrate all common digital logic functions by using Xilinx user-programmable gate arrays.”



That’s how the press release announcing the first FPGA in the “new” Xilinx second-generation XC3000 family started 28 years ago today. I think it’s really interesting to compare the “world’s most powerful” FPGA of 1987 with today’s smallest Xilinx Artix-7 FPGA, built with TSMC’s 28nm IC process technology.




Xilinx XC3020

Xilinx XC7A15T

Logic Cells



CLB Flip-Flops



Total Block RAM



DSP Slices



Analog block with A/D converters



Maximum Number of I/O Pins



Differential Multi-Gigabit Transceivers






Today, you can drop a full-featured MicroBlaze 32-bit RISC soft microprocessor core into a Xilinx Artix-7 XC7A15T FPGA and still have room for plenty of other system logic. A MicroBlaze processor core requires 600 to 4000 LUTs depending on configuration. Microblaze processors can run at clock rates exceeding 200MHz in an Artix-7 FPGA depending on configuration options. In other words, the MicroBlaze soft processor implemented in a Xilinx Artix-7 FGPA—even the smallest Artix-7 FPGA—will run *much* faster and deliver more processing performance when compared to the microprocessor cores in most microcontrollers. With more than 100kbytes of block RAM on chip, there’s even enough RAM in the Artix-7 XC7A15T FPGA to store and run sizeable embedded programs as well. You might not even need external RAM for many small embedded systems. You also might be able to skip adding analog circuitry by using the Artix-7 family’s on-chip XADC analog mixed-signal features.


Way back in 1987, FPGAs were clearly used as “glue logic” because they lacked the resources to implement entire systems. You certainly could not drop a microprocessor core into one. It’s a different decade, a different century, and a different millennium. FPGAs are system-level implementation devices now, even the small ones. You can fit any number of complete embedded systems into this smallest of Xilinx’s 28nm All Programmable devices. Just imagine what you might do with the bigger ones.


Fez and Tie.jpgXilinx was founded in early 1984 but the company’s first FPGA—the XC2064—was announced on November 1, 1985; that’s nearly 30 years ago. This ur-FPGA was the brainchild of Xilinx co-founder Ross Freeman; it was designed by Bill Carter; fabricated by Seiko in Japan; and marketed by the world’s first fabless IC vendor—Xilinx—as envisioned and co-founded by CEO Bernie Vonderschmitt. The first working devices powered up in September, 1985. Coincidentally, that’s 30 years ago this month. I discovered that it’s surprisingly hard to find one of these early, early programmable-logic devices at today’s Xilinx HQ. It’s surprisingly hard to find someone who even remembers seeing one of these chips in a package.


If I were Doctor Who, I’d jump in my TARDIS, go back in time 30 years, and pick one up. Alas, I’m not Doctor Who but I do have a TARDIS of sorts.


The Internet, this blog, and eBay are my TARDIS.



Tardis Key.jpg



I clicked over to eBay a couple of weeks ago, did a quick search on “Xilinx 2064,” and bingo. There was an unused 48-pin DIP with the unmistakable Xilinx logo for sale by a vendor named “ACP Surplus” in Santa Ana, California. The price was $5.97 plus $5 shipping. (Orignal unit price in 1985: $55 to $80.) The eBay product photo showed a date code from early in 1988 but it’s still the original Bill Carter design, give or take a production tweak or two. A few more mouse clicks and the order was placed.


Here’s the entire block diagram of that original Xilinx XC2064 FPGA:



Xilinx 2064 Block Diagram.jpg



Xilinx XC2064 “Logic Cell Array” Block Diagram



Note that the configurable logic blocks (logic cells) form a regular 8x8 array—thus the original name for the device, a “Logic Cell Array.” Today, we know the descendants of this ur-programmable-logic-device as FPGAs.


Comparing the specs of the original XC2064 FPGA with the largest FPGA being shipped today, the 20nm Xilinx Virtex UltraScale XCVU440, is an eye-opening experience. Here are some key macro-level comparisons:




Xilinx XC2064-33 48-pin DIP

Xilinx XCVU440

Logic Cells



CLB Flip-Flops



Total Block RAM



DSP Slices (GMACs/sec)

0 (0)

2880  (4268)

Maximum Number of I/O Pins



Differential Multi-Gigabit Transceivers





We’ve definitely made some progress in 30 years. Today, you can instantiate complex, sophisticated systems entirely in one of today’s FPGAs and many Xilinx customers do.


My miniature time capsule arrived yesterday by TARDIS post from Southern California:



Xilinx 2064 48-pin DIP.jpg



Xilinx XC2064-33 in a 48-pin DIP



I certainly don’t plan to plug this antique chip into a system. Instead, I’m going to store it next to a few other artifacts in my warehouse.


Note: If you’d like to read about the founding of Xilinx and the development of the world’s first FPGA, see last year’s blog post “Happy 30th birthday, Xilinx! (Free downloadable origin story, courtesy of SemiWiki’s new Fabless book)” where you can download the Xilinx chapter from Daniel Nenni’s and Paul McLellan’s book “Fabless: The Transformation of the Semiconductor Industry.”



Deep neural networks (DNNs) deliver impressive results in various cognitive tasks such as object detection and image classification. However, these networks contain a huge number of parameters and the evaluation of such models is computationally expensive. Von Neumann computers implement DNNs by storing a large number of weight parameters in external memories time-sharing processing elements. This traditional DNN architecture requires inefficient data transfer between parameter-storing memories and processing units leads to processing bottlenecks and many, many power-hungry I/O operations. Researchers at Incheon National University have developed a neuromorphic computing system designed from the ground up for energy-efficient evaluation of large-scale neural networks. The computing system consists of a non-conventional compiler, a neuromorphic hardware architecture, and a space-efficient microarchitecture based on a Xilinx Artix-7 100T FPGA.



Neuromorphic Computing System.jpg



Neuromorphic Computing System Mapped to Xilinx FPGAs




Adam Taylor’s MicroZed Chronicles Part 100

by Xilinx Employee on ‎09-14-2015 09:30 AM (1,414 Views)


By Adam Taylor





Untitled stone sculpture by Stonecoat Ind. Installed in 1986 at Granville Street Bridge, Fairview, Vancouver, Canada.


By Jess from Canada





About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.