05-14-2013 01:29 AM
I have a simple register read/write/reset test interface code (in VHDL) that I want to link up with my top level processing system 7 wrapper code. I want to use the AXI bus protocol to do read/write/reset to a register. Effectively, my test interface is the slave and the processing system 7 is the master. I use the SD card to load an image of Zynq Linux onto the Zynq-7000 chip. I load the Linux kernel module device driver from UG873 (blink.ko) dynamically onto the running Kernel. I then use a modified Linux-based application software (linux_blinkled_app.c) to do register read/write/resets.
My system specs are:
Windows XP 32-bit
ZC706 evaluation board
I have gone through the Blink example project (UG873 and UG683) and it says you must use the CIP wizard in XPS to create a custom interface with your component. CIP generates two VHDL templates (user_logic.vhd and 'your_component'.vhd) in which you have to add custom ports and custom code...all the AXI interfacing is sorted out for you in the templates/CIP wizard (you get an AXI interconnect, AXI slave and AXI master). I add a chipscope to look at the signals/transactions going through the AXI bus. But when I load the bitstream and run the software, I get only one complete read transaction in chipscope and the Linux OS hangs.
My question is, do you have to use this CIP wizard to interface with the AXI or can you do it manually? And how would you set it up manually (VHDL code)?
05-14-2013 06:44 AM
In chipscope, double check that your rresp signal on the read is 0 and that there is a good rvalid rready handshake. Which side of the interconnect are you probing? Make sure to check the processor side.
Yes, you can do it manually without CIP wizard, but it'll probably take a bit more verification time/debugging.
If I were doing it, though, I'd start here:
05-17-2013 02:59 AM
I have decided to go down the CIP wizard route for now.
But it is quite difficult to work out the address system. My component has a single address port 'reg_addr : in std_logic_vector(7 downto 0)'.
My question is how can I pass Bus2IP_Addr (std_logic_vector(0 to 31)) to reg_addr in the user_logic.vhd template?