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Visitor tkdon
Visitor
5,075 Views
Registered: ‎04-05-2011

ADC/DAC on Spartan 3E and accessing using Microblaze

Hello,

 

I was advised to start a new thread/post for this rather than using an old one, so here it is.

 

Basically, I wrote my own driver in VHDL  for the ADC and DAC on the Spartan 3E starter board (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,793&Prod=S3E1600) , where the former is very similar to the one in adc2.rar posted in http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Spartan-3E-Starter-Kit-Board-ADC/td-p/8548 .

 

However, I want to use the ADC and DAC with the Microblaze processor, and three questions arises, which I hope someone may be able to help answering.

 


1) I'm actually a bit puzzled about how to connect the DAC and ADC to the Microblaze, since I´d assume I'd still have to use some sort of FSL/OPB/PLB bus to somehow talk to the device using the ADC and DAC drivers. What to do here?

 

Apart from the usual clock (sck in this case), and reset, my ports for the ADC are declared as:

 

- convert (in) input to tell the adc to start sampling.

- oe_adc (in) output enable for adc.

- spi_miso (in) data extracted by the adc chip

- adc1 (out) stores 12 bits of data from spi_miso (sampled by one of the adc channels)

- adc2 (out) stores 12 bits of data from spi_miso (sampled by the other adc channel)

- cs_amp (in) chip select for amplifier

- spi_mosi (out) output to amplifier used to program the gain

- gain (in) defines the amp gain

 

2) Also, does anyone have a simple sample code in C to communicate with the ADC (i.e. read data into a variable etc.) ?

 

3) I notice that the timing requirements of the DAC allows me to run the SPI bus at 50 MHz, while the ADC does not. Is the reason for the counters in adc2.vhd in adc2.rar of the above mentioned thread to establish some sort of delay?

My design originally used a clock divider instead though... but I have modified it to the same as adc2.vhd.

I have searched this forum, and did find something regarding question 2: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/ADC-DAC-Tutorials/td-p/44909 but it seems like they used the already available delta-sigma ADC IP core in XPS for this...

 

Thanks for any hints (yes I'm new to Xilinx)

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2 Replies
Teacher eteam00
Teacher
5,072 Views
Registered: ‎07-21-2009

Re: ADC/DAC on Spartan 3E and accessing using Microblaze

1) I'm actually a bit puzzled about how to connect the DAC and ADC to the Microblaze, since I´d assume I'd still have to use some sort of FSL/OPB/PLB bus to somehow talk to the device using the ADC and DAC drivers. What to do here?

OK, in this question you have identified yourself as a software designer (as opposed to a hardware designer).  If my impression is (more or less) correct, you have much too much to learn to guide you through your design by way of forum posts.  Please consider finding a real, honest-to-goodness hardware designer to help you in this project.  There is (practically) no end to the number and scope of questions and problems lurking over the horizon.  I hope you are experienced and humble enough to know how much you don't know.

 

Does your MicroBlaze design, as it stands now, include any ports for reading and writing "external" (external to the MicroBlaze) logic signals?  If so, then clone this port logic and use a new (and unallocated) address for the cloned port.

 

Then you need to use logic signals to connect IO pins to the newly cloned MicroBlaze port.

Apart from the usual clock (sck in this case), and reset, my ports for the ADC are declared as:

We're missing important context for the term 'port'.  There is no ADC in the FPGA design.  Are you describing VHDL module ports, MicroBlaze signal ports, a simulation model port, or ???

 

In your list of 'port signals', you seem to have input signals and output signals mixed together without sufficient differentiation.  Some added context would be helpful to the forum audience, and might help you clarify your thoughts as well.

2) Also, does anyone have a simple sample code in C to communicate with the ADC (i.e. read data into a variable etc.) ?

Sorry, can't help you.  I'm too much of a low-level hardware nerd.

3) I notice that the timing requirements of the DAC allows me to run the SPI bus at 50 MHz, while the ADC does not. Is the reason for the counters in adc2.vhd in adc2.rar of the above mentioned thread to establish some sort of delay?

My design originally used a clock divider instead though... but I have modified it to the same as adc2.vhd.

Again, you are showing your lack of hardware depth.  Clock frequency is not a matter of delay, in the context of ADC and DAC interfaces.

 

Hardware designers (myself included) will often merge, into their designs, logic blocks which others have written.  But you absolutely, positively must understand how the block works so that you can customise the block to your specific needs and constraints.  You really have to get your fingers 'dirty' when designing in the hardware world.  Even though you are using a MicroBlaze controller core as the centre of your design, the problem at hand is more hardware than software.

 

I'll give you credit for asking these questions before you've 'built' your design.  Many hardware newbies continue with their design work, picking blocks from here and there on the internet to build a frankendesign, and when it doesn't work they will ask (oftentimes in these same forums) for help with debugging.  In such cases, the help they needed first and foremost is in designing rather than debugging.

 

The question needs to be posed:  After you think your design questions have been answered, how do you plan on debugging your design without a knowledge and thorough understanding of the hardware (in general) and your design ('borrowed blocks' included, in particular).

I have searched this forum, and did find something regarding question 2: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/ADC-DAC-Tutorials/td-p/44909 but it seems like they used the already available delta-sigma ADC IP core in XPS for this...

Ouch!  An external SPI ADC bears a resemblance to a delta-sigma ADC IP core only at the most abstract level.  You need to understand the low-level nitty gritty details.

 

-- Bob Elkind

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Visitor celojan
Visitor
4,996 Views
Registered: ‎02-07-2011

Re: ADC/DAC on Spartan 3E and accessing using Microblaze

LTC1407A-1 Im trying to do the same work.

First that i learn is that the ports and the UCF shuold be configure correct. Read the manuals of LTC1407A-1 and the SPI LTC6912-1. Undestand the graphics of spi comunicacion of both devices.

 

Then Inclide the SPI core and connect to PLB bus. All ports are external. The SCK should be configured 1:32 in the core.

Then activate the buffers to send and recived.

 

Detail the ports in the UCF file, remenber that the ss signal should be an array of 2 elements.

 

Then import the project from EDK to SDK. Create a new platform stand alone in SDK, then include your code. Im trying to develop one C code for my thesis.......!!!!!

 

Some expert xilinx programer that help US...!!!! Its posible get adc with Microblaze...but take some time yet...!!!

 

Any expert help with some c code for this problem..!!!

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