ARTY Artix-7 Kit Board Interface Files

[mpjones2015]

Hello,

I recently bought an ARTY dev board and downloaded the Vivado Design Suite with the included voucher. Vivado contains board files for the AC701, but not the ARTY board. Is there a way to download ARTY specific board interace files?

Thank you.

[mpjones2015 · Accepted solution]

Turns out they are on the Digilent website not the Xilinx website. You can find them on this page: https://reference.digilentinc.com/doku.php?id=arty#design_resources

[pratham]

@mpjones2015 Not only board files, for all documentation, user guide and design files are on digilent webpage. If you click on any of the documentation link below here it would take you to digilent arty webpage. 

http://www.xilinx.com/products/boards-and-kits/arty.html#documentation

[thua]

Hello,

 The Arty kit board file obtained from Digilent has xilinx part xc7a15ticsg324-1L being specified. I have changed the part number in Vivado project setting as well as in the board.xml and part0_pins.xml to reflect the correct one (Xilinx license obtained was device locked to xc7a35tcsg324). However, I am still getting "Failed to obtain synthesis license and/or invalid device" error message. Has anyone experienced similar issue? Could you please provide inputs to resolve this issue.

Thanks in advance

Ted

[mpjones2015]

Hmm, so this page: https://reference.digilentinc.com/vivado:boardfiles2015 has two different versions of the board files. The link at the top of the page goes to a file called board_files_09252015. The link at the bottom of the page goes to a file called board_files_06182015. The link at the top of the page is to the latest, correct package.

The documentation appears to still be a work in progress. There's been a lot of updates over the last couple of weeks.

[thua]

Problem has been resolved. Thanks 

[lemoutan]

Having been somewhat enticed by the web-server application video you posted on youtube (NF7ryZH8lxE), I bought a Digilent Arty board and was asked to download and install vivado. I installed the latest version, 2015.4 - (why wouldn't I?). Then I had to introduce the board to vivado with Digilent's board-files. So far so good. Then I try the 'out of the box' projects called BSD, GPIO and XACD_Demo and none of them work. Loads of critical warnings and plain warnings. It looked much too scary to pursue. Upon examination of the error messages from the create_project.tcl script I see:

ERROR: This script was generated using Vivado <2015.3> and is being run in <2015.4.2> of Vivado.
       Please run the script in Vivado <2015.3> then open the design in Vivado <2015.4.2>.
       Upgrade the design by running "Tools => Report => Report IP Status...",
       then run write_bd_tcl to create an updated script.
ERROR: [BD 5-229] Please open or create a block design first.
ERROR: [Common 17-39] 'get_bd_designs' failed due to earlier errors.

So I find I have to download and install 2015.3 as well. Another afternoon gone. Sigh. OK, these things happen. Naturally, the first time I do as instructed I find I've forgotten to also introduce the digilent board files to this earlier IDE. SO I have to cleanup, introduce and start again. Hah! This time I get a lot further - lots of nice diagrams seem to get generated and drawn - but notice a couple of warnings:

## create_root_design ""
WARNING: [BD 41-176] The physical port 'di' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'di' specified in the portmap, is not found on the block! 
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
Wrote  : <YadaYadaYada/Arty-master/Projects/BSD/proj/bsd.srcs/sources_1/bd/system/system.bd> 

But as yet I've no way of knowing if I should care about these, never having faced vivado before. Anyway, I'm now stuck as - because I've never ever used vivado before (and am kind of relying on these getting started with arty projects to help in that regard) the instruction then open the design in Vivado <2015.4.2> means nothing to me since starting up 2015.4.2 offers no such 'open design' option from any visible menu or toolbar/toolpanel.

I'd normally assume that if I was supposed to open the project, it would say so. But as I don't know how to open a vivado design, all I can do is open a project. So I experiment with that, feeling sure it's the wrong thing to do, but what else is there? Nothing disastrous seems to happen, and the Tools/Report/ReportIPStatus is there, so I elect that. Again, a little happens and an IP Status Panel opens up, showing 17 revision changes. But there's no sign of a write_bd_tcl script anywhere in the neighbourhood tree of the project folder. So if I go that way, I get stuck again. But I'm really not sure I should have taken that 'open project' (as opposed to design) route in the first place!

Is there a file .extn meant for a design?

Presumably I'll have to do the same things (whatever they turn out to be) for the GPIO and XADC_Demo project-building scripts.

BTW are these conversions from v2025.3 scripts to v2015.4 scripts once only, or do you have to do them every time you might want to base a new project on them? Please bear in mind that I've no idea what vivado is doing or what it's methodology is - I'm just blindly doing as I'm told here!

I'm no stranger to IDEs btw, but I've never encountered anything quite so - umm - flexible, I suppose, as vivado. Microsoft's developer suites are complicated enough.

[oe7aft]

Hi,

I had also the version 2015.3 / 2015.4 issue but I have simply solved it in the following way. May be is not the most elegant one but the design csn be then synthesized without any error:

in script "create_project.tcl" simply replace line 114:

#set scripts_vivado_version 2015.3
set scripts_vivado_version 2015.4

in script  "\src\bd\system.tcl" replace line 13:

#set scripts_vivado_version 2015.3
set scripts_vivado_version 2015.4

best regards

E.

[lemoutan]

Apologies for the late response. It did not occur to me that this forum was an opt IN for responses and so had no idea you'd answered! [You have to subscribe to a whole RSS, right?]. Oh - I see an "email me when type checkbox", never mind :)

ANYway. Having already gone the 'long way round' by doing something with vivado 2015.3 so that 2015.4 wouldn't have those problems, I'm not exactly sure how your tcl script suggestion is to be applied. As I said in the post, I rather warily opened the project - despite being told to open the design, which I think I see now could have meant "Now open the project in vivado 2015.4 and, inside that, open the design"). So I may try your suggestion on another project (probably the XADC one, which I think will be the more enlightening if it would but work out of the box!), but I imagine I'll still get stuck at the same place where I'm being told to run a tcl script which just plain ain't there!

Thanks for your input. I'll get back to you!

[lemoutan]

I no longer know what's going on. Without having updated any sources (to the best of my knowledge) the errors now appear to have gone away. That missing tcl script I mentioned earlier isn't mentioned in any log messages any more, so what that was all about I guess I'll never know. There are still loads of warnings and critical warnings, but apparently we are to ignore these, as before.

There look to be fairly serious (they're in red) timing issues. It seems possible to generate bitstreams though, and program the device. Apparently the timing problems are known about (at digilent) and they'll get around to changing the connections of some clock and reset designery at some stage. Have not tried the GPIO project but only redone the BSD and XADC_Demo (in viv2015.4.2 and 2016.1).

[sm7ed]

I think a better place to download the board files would be this repository: https://github.com/Digilent/vivado-boards