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Participant
Participant
517 Views
Registered: ‎09-12-2018

Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Artix-7FPGA ac701评估工具包承载了一个基于德州仪器(TI)ucd90120a电源排序器和监视器的电力系统。这些电源控制器需要一个XML配置文件才能在这些平台上正常工作。ac701提供了预先编程的这个XML文件和适当的设置。附加的XML文件(ac 701_revb_ti_xml.zip)可用于将ap 701评估工具包上的电源控制器重新编程到工厂默认配置。只需重新编程电源控制器的XML文件。

现在,我需要重新编程,根据 AR# 57452 应答记录中列出的编程步骤。

第二步:将USB到GPIO适配器连接到系统板和主机,然后启动系统;要了解如何从ti订购USB到GPIO适配器,请与Xilinx支持联系。

问题一:请问如何订购适配器?之前买的AC701套件里面没有找到合适的连接器,后续的连接及下载问题要注意些什么?

问题二:在以后的设计中,可能需要对电源上电顺序有一定的要求,请问我们用户可以根据自己的需求编写配置文件吗?该如何编写呢?

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Xilinx Employee
Xilinx Employee
489 Views
Registered: ‎06-21-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Hi jt779862810,

Question 1: How do I order an adapter? I did not find a suitable connector in the previously purchased AC701 kit. What should I pay attention to in subsequent connection and download problems?

Answer: If you want to program the XML file into the UCD90x device, you'll need TI's USB Interface Adapter:
https://www.xilinx.com/support/answers/54022.html

Question 2: In the future design, there may be certain requirements for the power-on sequence. Can the user write a configuration file according to their own needs? How to write it?

Answer: Yes, you can do that with TI's software.

Thanks,
Andres

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Participant
Participant
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Registered: ‎09-12-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Thank you for your reply! when I read the AR# 37561 Records, there is a Caution:

Caution: Xilinx does not recommend changing any of the parameters on the power rails from the factory settings as the board components could be inadvertently damaged. 

Could I change these settings without damaging the development board, what should I pay attention to?Thank you!

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Xilinx Employee
Xilinx Employee
456 Views
Registered: ‎06-21-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Hi jt,

I thought you wanted to create a new XML for your own board!

I agree that you shouldn't change the rails from the factory settings; which rail did you want to change and why?

Thanks,
Andres

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Participant
Participant
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Registered: ‎09-12-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

XDMA design on the AC701 board, using the driver provided by Xilinx. The generated binary file is written to flash, and the FPGA is loaded from flash when power is turned on. Restart the boot, the DMA device is not detected during the BIOS self-test, so it is necessary to shorten the FPGA power-on time, so that the FPGA has been loaded before the BIOS self-test. So I need to change the power configuration。Thank you !

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Xilinx Employee
Xilinx Employee
442 Views
Registered: ‎06-21-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Oh, I get it now! So you'd keep the same power levels and ramp up and down, just delay the start of it.

I've never seen any customer do it, but sounds reasonable. Maybe @travisc has experience on this?

Thanks,
Andres

 

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Moderator
Moderator
413 Views
Registered: ‎04-12-2017

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Hello @jt779862810 

There are other methods to achieve short time of configuration. 

1. Tandem Configuration

2. Bitstream Configuration

3. Increasing clock speed of configuration

Make sure you have tried all until you Fidel with power supplies.

Thank you

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Participant
Participant
400 Views
Registered: ‎09-12-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

Hello!

I looked at the schematic of the AC701 board. I checked the connection relationship between the PMbus connector and the FPGA, power controller U8, and U9. When I configure the power controller using the Firmware & Configuration Download Tool (refer to AR# 57452). The configuration details are configured directly through the PMBUS connector J2 for U8U9 or is it controlled by the FPGA? If an FPGA is used, is the IIC bus used? How does the FPGA allocate the IIC bus?

Below is the J2 schematic and the connection I have organized.Thank you!

QQ图片20190527164156.png
QQ图片20190527164351.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-21-2018

Re: Artix-7 FPGA AC701 Evaluation Kit - Master XML File for TI Power Controller

The configuration details are configured directly through the PMBUS connector J2 for U8U9 or is it controlled by the FPGA?

- The details are for the J2 connector with a TI dongle.

If an FPGA is used, is the IIC bus used? How does the FPGA allocate the IIC bus?

- The connection of PMBUS_CLK and PMBUS_DATA to the FPGA are provided, but I couldn't find any example design that uses them. The only provided method to update the U8 & U9 is through the J2 connector.

Thanks,
Andres

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