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Visitor
Visitor
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Registered: ‎06-04-2019

Capture and read parellel LVDS data

Hello community,

Right now I am working with ARTY-A7 FPGA board I want to interface this board with EVM ADS-5402 adc evaluation bord.

I am using vivado tool for simulation and hardware debuging process.

For my genralization,I sucsessfully generated 1 bit lvds data through ARTY-A7 FPGA board using IBUFG and OBUFG buffers.

My aim is to capture and read multiple parellel LVDS data from EVM ADS-5402.
as I am new too FPGA I am confused which methodology I should use.

with little bit googling I come across these two sollutions which are wether I use buffers or
I have to apply serializer deserialzer block to read and capture multiple parellel LVDS data through EVM ADS-5402.

I want to capture and read parellel LVDS data from EVM ADS-5402 evaluation board through ARTY-A7 FPGA board.

Hoping for any guidance or solution from anyone,

Thanks in advance !!

Regards,

Hiral Nikumbh

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Xilinx Employee
Xilinx Employee
304 Views
Registered: ‎06-21-2018

Re: Capture and read parellel LVDS data

Hi Hiral,

Not sure I understand your questions, but I'd like to help you.

You'll have 12 LVDS pairs for the digital value of your sample. You just need to use them as a bus on your RTL code.

Thanks,
Andres

 

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