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Visitor
Visitor
10,495 Views
Registered: ‎04-16-2014

Change 7seg display on clock

Hello, I have a homework: to make some verilog code for Nexys 2 board. The 7 seg display should show digits that change on clock. I make a clock divider because the default clock is 50Mhz. With a counter I am trying to display the digits. I don't know that the code works because I don't have a board at home and I want to know if this is corrent or not.


This is what I made:

 

[code]

module temacidlab(input clock,
      output reg clock_1Hz,
      output reg counter1,
      output reg counter2,
      output reg [7:0] seg
    );

always @ (posedge clock)
begin
 counter1 <= counter1 + 1;
 if(counter1 == 50000000)
  clock_1Hz <= clock_1Hz + 1;
end

always @ (posedge clock_1Hz)
begin
 counter2 <= counter2 + 1;
 case(counter2)
  0 : seg = 8'b10011111; // 1
  1 : seg = 8'b00001001; // 9
  2 : seg = 8'b00001101; // 3
  3 : seg = 8'b00000011; // 0
  4 : seg = 8'b10011001; // 4
  5 : seg = 8'b00000011; // 0
  6 : seg = 8'b00001001; // 9
  7 : seg = 8'b10011111; // 1
  8 : seg = 8'b01000001; // 6
  9 : seg = 8'b00000011; // 0
  10 : seg = 8'b00000011; // 0
  11 : seg = 8'b10011111; // 1
  12 : seg = 8'b10011111; // 1
  default: counter2 = 0;
  endcase
end
 

endmodule[/code]

 

Thanks for your further help.

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5 Replies
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Professor
Professor
10,478 Views
Registered: ‎08-14-2007

Re: Change 7seg display on clock

The accepted method of seeing if your code works is to simulate it, not to throw it onto the forums.  I can see issues with the code, but it would teach you a lot more to understand how to debug your own code using simulation.

-- Gabor
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Visitor
Visitor
10,468 Views
Registered: ‎04-16-2014

Re: Change 7seg display on clock

Can you give me a hint? I did the simulation and I saw that something is wrong.

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Highlighted
Professor
Professor
10,457 Views
Registered: ‎08-14-2007

Re: Change 7seg display on clock

Here's a hint:

 

How many bits does your counter1 need to count up to 50000000?  How many bits does your counter1 actually have?

 

Here's another one:

 

If you don't need to place a signal on the pins of the FPGA, it should not be a port in the top level code.  Intermediate results, variables like counter1, should be local to the module and not in the port list.  So instead of output reg counter1,

after the port declarations, just declare reg counter1.  Oh, and make sure you give it enough bits to count up to 50000000.

-- Gabor
Highlighted
Visitor
Visitor
10,453 Views
Registered: ‎04-16-2014

Re: Change 7seg display on clock

Hi, thanks for your hints. I rewrote the code. Here it is:

 

module frquency_divider_by10 (input clock,
          input reset,
          output reg [7:0] c,
          output [3:0] an);

reg clock_mic ;
reg [3:0] counter;
reg [27:0] i;

initial counter = 0;
initial i = 0;

always @ (posedge clock) begin

  if (i<240000000)
   i <= i + 1;
  else
   i <= 0;
 end

always @ (i) begin

  if (i<120000000)
   clock_mic <= 1;
  else
   clock_mic <= 0;

 end

always @ (posedge clock_mic) begin
 if(reset)
  counter = 3'b0;
 else
  counter <= counter + 1;
 case(counter)
  0 : c = 8'b10011111; // 1
  1 : c = 8'b00001001; // 9
  2 : c = 8'b00001101; // 3
  3 : c = 8'b00000011; // 0
  4 : c = 8'b10011001; // 4
  5 : c = 8'b00000011; // 0
  6 : c = 8'b00001001; // 9
  7 : c = 8'b10011111; // 1
  8 : c = 8'b01000001; // 6
  9 : c = 8'b00000011; // 0
  10 : c = 8'b00000011; // 0
  11 : c = 8'b10011111; // 1
  12 : c = 8'b10011111; // 1
  default: c = 8'b11111111; 
  endcase
end

endmodule

 

In simulation it works. Will it work on the board too?

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Highlighted
Professor
Professor
10,450 Views
Registered: ‎08-14-2007

Re: Change 7seg display on clock

I think it might work, but what bothers me is that you have created a clock using a gate.  clock_mic is not coming from a clocked process.  So when "i" changes state, it's possible that there could be glitches as the various bits of "i" reach the gate at different times.  Normally in a synchronous system this is not a problem, but when you then use that glitchy signal as a clock it can result in unexpected problems.

 

For such a low frequency, there's no need to use a 50% duty cycle for the clock.  So if you really want to use a slow clock rather than keeping everything synchronous and just having a clock enable, then you would be better off just using the MSB of "i" as the clock even though it doesn't have a 50% duty cycle.  Otherwise if you really want that 50% duty cycle, I'd suggest using a clocked process for clock_mic - i.e. replace always @ (i) with always @ (posedge clock).

-- Gabor