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Explorer
Explorer
521 Views
Registered: ‎12-07-2018

Debug on ZCU106 Eval: "no supported debug core"

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Hello, I am new to Xilinx and am using the ZCU106 Eval board to test out the Aurora 64b66b IP core. I have went througt the Video Design Suite Tutorial Programming and Debugging UG936. I am able to get through Lab 1, but the problem is in Lab 5 when I program the device. I get the following in the TCL window:

program_hw_devices: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 6202.184 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xczu7_0] 0]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xczu7 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0

I think this is relating to why I don't see the hw_ila debug cores in my design.

Can you please help me troublshoot this problem.

programming.jpg

 

Thank you,

Joe

 

 

 

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Contributor
Contributor
357 Views
Registered: ‎11-18-2012

Re: Debug on ZCU106 Eval: "no supported debug core"

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PS_REF_CLK is a dedicated pin for PS. So you cannot connect to dbg_hub .
After checking the constraints, INIT_CLK_P seems to be usable as free running.


Look for INIT_CLK_P in Schematic.
If you follow that connection, you should have a BUFG.
Select the Net connected to the BUFG output and check the Net Name.
Modify the Net Name in the constraints.

The figure below is a sample.

In this example, it looks like this.
connect_debug_port dbg_hub/clk [get_nets i_design_1 /design_1_i /zynq_us_ss /clk_wiz_0 /inst/clk_out1]

cap.PNG

9 Replies
Contributor
Contributor
496 Views
Registered: ‎11-18-2012

Re: Debug on ZCU106 Eval: "no supported debug core"

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As mentioned in the message, a common problem is clock problems.

Try connecting a stable clock to dbg_hub immediately after starting configuration.

https://www.xilinx.com/support/answers/64764.html

 

Moderator
Moderator
469 Views
Registered: ‎11-09-2015

Re: Debug on ZCU106 Eval: "no supported debug core"

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Hi @joe306 

Most of the time this happen because users are using clock from the Zynq/ZynqMP processor. But if you are only programming the PL the processor will not be configured and thus the clock will not be initialized.

The solution is to run a simple hello world in SDK to initialize the Processing System and then to refresh the view in vivado

This is something I am covering in my Video Series 31 – Debugging a Video System using an ILA

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
445 Views
Registered: ‎12-07-2018

Re: Debug on ZCU106 Eval: "no supported debug core"

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Hello, thank for responding to my message. Here is a view of the clk of the dbg_hub:

 

ila_view2.jpg

I looks like the clk is being fed by the user_clk_i output of the auroa_64b66b_0_support block.

 

Is that a free running clock?

 

Thank you,

Joe

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Explorer
Explorer
443 Views
Registered: ‎12-07-2018

Re: Debug on ZCU106 Eval: "no supported debug core"

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Hello, is there a tutorial how to do a "simple Hello World in the SDK"?

Thank you,

Joe

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Moderator
Moderator
436 Views
Registered: ‎06-05-2013

Re: Debug on ZCU106 Eval: "no supported debug core"

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We do have tutorial based on ZCU102 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1209-embedded-design-tutorial.pdf 

You can follow the same to run hello world on ZCU106. 

-Harshit 

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Explorer
Explorer
434 Views
Registered: ‎12-07-2018

Re: Debug on ZCU106 Eval: "no supported debug core"

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I just noticed that in the xdc file the line:

 

connect_debug_port dbg_hub/clk [get_nets user_clk_i]

The net name user_clk_i is not tied to anything, so I believe it is free running.

I need to find a clock to connect it to. How about the PS_REF_CLK pin R24?

 

Thanks,

Joe

 

 

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Explorer
Explorer
427 Views
Registered: ‎12-07-2018

Re: Debug on ZCU106 Eval: "no supported debug core"

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I don't know the TCL command to connect the PS_REF_CLK pin R24 to the dbg_hub/clk. Is it possible?

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Highlighted
Contributor
Contributor
358 Views
Registered: ‎11-18-2012

Re: Debug on ZCU106 Eval: "no supported debug core"

Jump to solution

PS_REF_CLK is a dedicated pin for PS. So you cannot connect to dbg_hub .
After checking the constraints, INIT_CLK_P seems to be usable as free running.


Look for INIT_CLK_P in Schematic.
If you follow that connection, you should have a BUFG.
Select the Net connected to the BUFG output and check the Net Name.
Modify the Net Name in the constraints.

The figure below is a sample.

In this example, it looks like this.
connect_debug_port dbg_hub/clk [get_nets i_design_1 /design_1_i /zynq_us_ss /clk_wiz_0 /inst/clk_out1]

cap.PNG

Explorer
Explorer
299 Views
Registered: ‎12-07-2018

Re: Debug on ZCU106 Eval: "no supported debug core"

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Thank you very much. I greatly appreciate your help. 

 

Have a great day. Joe

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