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Visitor
Visitor
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Registered: ‎01-29-2019

Disable L2 Cache for CPU1 Zynq7000 for AMP

Hi

I want to use the Zynq7000 of Zybo Z7 board for AMP mode. I am using Vivado SDK 2018.3.

The idea is to have two different instances of freertos running on each core (CPU0 and CPU1) while sharing data through OCM. (freertos version 1.2). I have created the two projects with the SDK assistant configuring them with OS platform: freertos_10_xilinx

The linker files were configured in the SDK so that RAM for CPU0 and CPU1 are located in different memory spaces.

I am taking as guide XAPP1079, with the difference that instead of two baremetal applications I am using two freertos applications.

QUESTION: Both apps are working as expected rigth now  but: In the Xapp1079 they state that L2 Cache for CPU1 should be disabled, and it is made with some changes in the Standalone BSP for the CPU1, the thing is that I am using freertos on CPU1 so I can´t use the provided BSP for the Xapp1079 example. How can I disable the L2 cache RAM for the CPU1 in this case? Anyway, considering that rigth now the apps are working as expected, it is mandatory to disable this cache?

Thanks for your help

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Scholar
Scholar
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Registered: ‎04-13-2015

@fandres17 

From my understanding of the caches, once the L2 is enable it's used by both cores.  Seems to me the App Note is trying to say indirectly (a bit ackwardly) that if cache maintenace is needed in your app (that's cache flushing or invalidation) then core #0 must be the one performing the operation. Why? Because maintenance ops on the L2 involves registers accessible by both cores (L1 ops are local) meaning a clash if both cores perform maintenance wothout an exclusive access protetion mechanism.

Have you ever consider using SMP instead of AMP? - SMP is much easier to use.

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Visitor
Visitor
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Registered: ‎01-29-2019

Thanks for your help. Do you know if Freertos performs (internally) any of these L2 cache maintenance ops?

Would you recommend any OS configuration for SMP?

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