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Observer
Observer
7,587 Views
Registered: ‎07-13-2008

Hitech's Virtex-4 Embedded Tri-mode Ethernet MAC does not work when downloading to board

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Hi guys,

 

How are you ?

 

Recently, I am using Hitech global Virtex-4(xc4vfx60-10ff1152) board to implement Ethernet.

 

This is what I did:

I'm referring to the Example Design that is generated automatically via Coregen (for V4 Embedded TEMAC)

And then creat new top module, add DCM to set clocks, edit IBUFG, IBUF, and set constraint file to my V4 board.

And I modify the testbench to the modified project, and timing simulation is perfect.

However, when downloaded to board, I use traffic generator to send packet, I saw nothing, even the Receive led doesnot blink.

And I use chipscope to observe, and see nothing.

Can anyone give me a hand about this issue?

 

And I am not for sure about such constraint:

1. reset signal: is it system reset or phy_reset? Beacause there is only system reset in the board.

2. gmii_rx_clk: the constraint location is in the bank 4 together with other global clks, but for gmii_tx_clk, it is in the bank 12. I think they are should be in the same bank because they are all Ethernet PhY clock rather than global clock.

 

I would appreciate any help and insights in solving this issue if anyone here has ever gotten this to work.

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Observer
Observer
8,273 Views
Registered: ‎09-24-2008

Hi Ryon,

 

I've worked on similar board from Hitech and having same FPGA (as far as I remember). The simulations work fine. I would recommend you to check the pin contraints against the one given in the Board reference manual. They have given the pin locations for all the signals. As far as I remember the pin contrainsts are correct for gmii_rx_clk and gmii_tx_clk. And the phy_reset and system reset are same. Again I would recommend you to verify the pin locations in the UCF file against the one given in the board reference document.

And try to add counter to count the clock frequencies viz. system clock, gmii_rx_clk, gmii_tx_clk and didsplay it on the LEDs. So when you download and connect the ethernet cable, you will see LEDs counting the frequencies. You can use similar approach to debug.

And one last thing, I actually faced problem with traffic generator. I used in diagnostic loopback mode to transmit a packet from  traffic generator and receive it back.

So just make sure that you ahev setup traffic generator correctly.

 

regards

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Observer
Observer
8,274 Views
Registered: ‎09-24-2008

Hi Ryon,

 

I've worked on similar board from Hitech and having same FPGA (as far as I remember). The simulations work fine. I would recommend you to check the pin contraints against the one given in the Board reference manual. They have given the pin locations for all the signals. As far as I remember the pin contrainsts are correct for gmii_rx_clk and gmii_tx_clk. And the phy_reset and system reset are same. Again I would recommend you to verify the pin locations in the UCF file against the one given in the board reference document.

And try to add counter to count the clock frequencies viz. system clock, gmii_rx_clk, gmii_tx_clk and didsplay it on the LEDs. So when you download and connect the ethernet cable, you will see LEDs counting the frequencies. You can use similar approach to debug.

And one last thing, I actually faced problem with traffic generator. I used in diagnostic loopback mode to transmit a packet from  traffic generator and receive it back.

So just make sure that you ahev setup traffic generator correctly.

 

regards

View solution in original post

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Observer
Observer
6,502 Views
Registered: ‎07-13-2008
Thank you so much, Mr Mehta!
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