Is there a default XDC file for "processing_system7_0" IP on ZC706 board?

[bhuang2]

Hi,

I am trying to learn to use Vivado 2013.1 to create a hello-world project for my ZC706 board.  My goal is to create a very simple system with only "processing_system7_0" IP and then run some trivial C programs.

So far, I have been following these steps in Vivado 2013.1 to create my system:

(1) I created a Vivado project that targets ZC706 board;

(2) I added a "processing_system7_0" IP to my system;

(3) I re-customized my "processing_system7_0" IP and configured preset of Zynq PS to use "ZC706 Development Board Template";

I was able to synthesize this design but failed to geneate the bitstream I want. Here are error messages:

Running DRC as a precondition to command write_bitstream

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 259 out of 259 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: USB0_PORT_INDCTL[1:0], USB0_VBUS_PWRSELECT[0:0], USB0_VBUS_PWRFAULT[0:0], M_AXI_GP0_ARVALID[0:0], M_AXI_GP0_AWVALID[0:0], M_AXI_GP0_BREADY[0:0], M_AXI_GP0_RREADY[0:0], M_AXI_GP0_WLAST[0:0], M_AXI_GP0_WVALID[0:0], M_AXI_GP0_ARID[11:0], M_AXI_GP0_AWID[11:0], M_AXI_GP0_WID[11:0], M_AXI_GP0_ARBURST[1:0], M_AXI_GP0_ARLOCK[1:0], M_AXI_GP0_ARSIZE[2:0], M_AXI_GP0_AWBURST[1:0], M_AXI_GP0_AWLOCK[1:0], M_AXI_GP0_AWSIZE[2:0], M_AXI_GP0_ARPROT[2:0], M_AXI_GP0_AWPROT[2:0], M_AXI_GP0_ARADDR[31:0], M_AXI_GP0_AWADDR[31:0], M_AXI_GP0_WDATA[31:0], M_AXI_GP0_ARCACHE[3:0], M_AXI_GP0_ARLEN[3:0], M_AXI_GP0_ARQOS[3:0], M_AXI_GP0_AWCACHE[3:0], M_AXI_GP0_AWLEN[3:0], M_AXI_GP0_AWQOS[3:0], M_AXI_GP0_WSTRB[3:0], M_AXI_GP0_ACLK[0:0], M_AXI_GP0_ARREADY[0:0], M_AXI_GP0_AWREADY[0:0], M_AXI_GP0_BVALID[0:0], M_AXI_GP0_RLAST[0:0], M_AXI_GP0_RVALID[0:0], M_AXI_GP0_WREADY[0:0], M_AXI_GP0_BID[11:0], M_AXI_GP0_RID[11:0], M_AXI_GP0_BRESP[1:0], M_AXI_GP0_RRESP[1:0], M_AXI_GP0_RDATA[31:0], FCLK_CLK0[0:0], FCLK_RESET0_N[0:0].

ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 259 out of 259 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: USB0_PORT_INDCTL[1:0], USB0_VBUS_PWRSELECT[0:0], USB0_VBUS_PWRFAULT[0:0], M_AXI_GP0_ARVALID[0:0], M_AXI_GP0_AWVALID[0:0], M_AXI_GP0_BREADY[0:0], M_AXI_GP0_RREADY[0:0], M_AXI_GP0_WLAST[0:0], M_AXI_GP0_WVALID[0:0], M_AXI_GP0_ARID[11:0], M_AXI_GP0_AWID[11:0], M_AXI_GP0_WID[11:0], M_AXI_GP0_ARBURST[1:0], M_AXI_GP0_ARLOCK[1:0], M_AXI_GP0_ARSIZE[2:0], M_AXI_GP0_AWBURST[1:0], M_AXI_GP0_AWLOCK[1:0], M_AXI_GP0_AWSIZE[2:0], M_AXI_GP0_ARPROT[2:0], M_AXI_GP0_AWPROT[2:0], M_AXI_GP0_ARADDR[31:0], M_AXI_GP0_AWADDR[31:0], M_AXI_GP0_WDATA[31:0], M_AXI_GP0_ARCACHE[3:0], M_AXI_GP0_ARLEN[3:0], M_AXI_GP0_ARQOS[3:0], M_AXI_GP0_AWCACHE[3:0], M_AXI_GP0_AWLEN[3:0], M_AXI_GP0_AWQOS[3:0], M_AXI_GP0_WSTRB[3:0], M_AXI_GP0_ACLK[0:0], M_AXI_GP0_ARREADY[0:0], M_AXI_GP0_AWREADY[0:0], M_AXI_GP0_BVALID[0:0], M_AXI_GP0_RLAST[0:0], M_AXI_GP0_RVALID[0:0], M_AXI_GP0_WREADY[0:0], M_AXI_GP0_BID[11:0], M_AXI_GP0_RID[11:0], M_AXI_GP0_BRESP[1:0], M_AXI_GP0_RRESP[1:0], M_AXI_GP0_RDATA[31:0], FCLK_CLK0[0:0], FCLK_RESET0_N[0:0].

INFO: [Vivado 12-3199] DRC finished with 2 Errors, 2 Warnings

INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.

ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

INFO: [Common 17-83] Releasing license: Implementation

ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

I assume these errors are related to missing constraints for my "processing_system7_0" IP but I am not 100% sure. Also, I wonder if the constraints are provided in the "ZC706 Development Board Template" or not. If not, is there a default XDC file somethere in Vivado for me to use? Or do I have to generate the XDC file myself?

Thanks!

Bin

[ashishd]

Hi @bhuang2 ,

You need to write the constraints to your .xdc file as per your design requirement. The issue you are facing seems to occur as some design files in your design are somehow got corrupted and resulting into error generating bitstream. 

You can create fresh project. Implement it and manually apply constraints in I/O planning layout. Then re-implement the design by saving the constraints and generate the bitstream.