03-24-2021 04:07 PM
I just need a sanity check.
In the KC705 Evaluation Board User Guide (UG810_KC705) there is a voltage named VADJ_FPGA, one named FMC_VADJ, one named VCC_ADJ and one named VADJ. I suspect these are all the same.
Is that true?
If so, how in the name of Quality Control did this document get published like this?????
* Table 1-30 identifies U17 as the source of VCC_ADJ. Nowhere else in the document is there a mention of VCC_ADJ
* Table 1-3 identifies VADJ_FPGA as the rail for Banks 12,13,16,17,18. The note for the table says: "see Power Managment" section.
* On Figure 1-34 in the Power Management section, there's a signal shown coming from U17; SURPRIZE!!! it's got yet a different name: VADJ. But there's no mention of VADJ_FPGA in that section.
Please confirm that these four voltages are, in fact, the same.
03-31-2021 04:52 AM
Hello @barryvjpl ,
In relation to VCC_ADJ, let us to confirm regarding this with the development team and get back to you then. As indeed, VCC_ADJ isn't included in the KC705 schematic either, so let's confirm this and get back to you then.
As you can see, U17 has the Vout of VADJ and then there is also Vadj_FPGA, so these are not the same, as Vadj_FPGA voltage is VADJ @10A, as you can see below:
VADJ_FPGA is connected to Bank 13 VCCO power rail pins. VCCO_13 is Bank 13 power supply.
Here some info in relation to the FMC_VADJ on KC705.
FMC_VADJ for KC705 can be 1.8V, 2.5V, or 3.3V. The default value for VADJ on the KC705 is 2.5V and FMC_VADJ rail is set to 2.5V when the KC705 is shipped to customers.
Voltage control is achieved as follows:
When the KC705 is powered on, the state of the FMC_VADJ_ON_B signal (wired to header J65) is sampled by the TI UCD9248 controller, U55.
By default, a jumper exists on J65, therefore the signal FMC_VADJ_ON_B is held low, ensuring U55 energizes the FMC_VADJ rail at power on.
The rail turn on decision is made at power-on time (based on the J65 jumper setting); removing J65 after the KC705 is powered up will not affect 2.5V power delivered to FMC_VADJ rail.
As per UG810, at power on, if no jumper is present on J65, FMC_VADJ_ON_B signal is set to high and the KC705 will not energize FMC_VADJ 2.5V at power on.
The user can then control when to turn on FMC_VADJ and to what voltage level (1.8V - 3.3V).
With FMC_VADJ off, the Kintex-7 FPGA will still configure and has access to TI controller PMBUS and VADJ_ON_B signal.
Users can develop code to command the FMC_VADJ rail to be set to something other than default (2.5V). That code would program the FMC_VADJ voltage level into U55.
The VADJ_ON_B signal can then be driven low by user logic, and the FMC_VADJ rail comes up at the new FMC_VADJ voltage level.
The responsibility to develop code to achieve this rests with the individual customer, however this can be adjusted manually using TI tools and the TI USB adapter.
Hope this helps.
03-31-2021 08:17 AM
So, VADJ_FPGA is simply VADJ passed through what I assume is a .005 ohm sense resistor. But, nowhere on the schematic is FMC_VADJ shown. VADJ is shown connected to the FMC connector, J22, so should I assume that VADJ is the same as FMC_VADJ?
All I'm really concerned about is setting my bank IO voltage to 3.3V.
04-06-2021 01:58 AM
Hello @barryvjpl ,
I've checked with the higher level experts and they have indicated that these voltages may be the same voltage but its not the same IO. Its part of the VADJ requirements of the FMC spec.
This info is available with VITA 57.4 FMC+ specification and unfortunately, Xilinx can’t give out the Vita spec information. If this is required, you would have to obtain this from the VITA 57.1 website and I believe this is not free, and requires to be paid for: http://www.vita.com/.
04-06-2021 09:08 AM
This still doesn't answer my fundamental question, and it has NOTHING to do with the FMC spec or anything else, it has to do with the disconnect between the Users guide and the schematic: I'm trying to understand the different names for what appear to be the same voltage. Specifically, I want to set my VCCO voltage for banks 12, 13, etc., which looks like VADJ_FPGA, to 3.3V. Based on sheet 39 of the schematic, VADJ_FPGA is derived from VADJ, through R576, which looks like a 4-terminal 0.005 ohm sense resistor.
I just want to know how to adjust VADJ_FPGA (or VADJ, I guess).
Here's the problem:
1) In the Users Manual, p14, "I/O Voltage Rails" Table 1-3 refers to VADJ_FPGA (which is what I want to adjust).
2) The note below the table says : "For more information on VADJ_FPGA, see Power Management"
3) The Power Management sections SAYS NOTHING about VADJ_FPGA. But it does talk about setting FMC_VADJ.
4) Nowhere else, neither the schematic nor any other section of the Users Guide mentions FMC_ADJ.
5) So I am GUESSING that what is called FMC_ADJ in the Users Guide is called VADJ on the schematic.
Please confirm my suspicions.
04-07-2021 09:24 AM - edited 04-07-2021 09:25 AM
If you would just like to know how to change vadj to 3.3 you will need to follow the directions in ug810 page 75. It requires you to program the TI UCD9248. Below is a quick description.
1. Power off KC705.
2. un-installed J65
3. Power on KC705.
4. open TI Fusion Digital Power Designer GUI
5. enter new value in Vout box.
6. write to hardware
7. store ram to flash.
8. Power off KC705.
9. installing the jumper at J65
10. Power up the KC705, validate VADJ.
04-07-2021 10:45 AM
I am looking for someone to confirm that VADJ, FMC_ADJ and VADJ_FPGA are the same voltage.
You have told me how to adjust VADJ. You have not confirmed that this is VADJ_FPGA. I'm pretty sure that this is the case, but the Xilinx documentation is just completely inconsistent.