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Visitor vinayps
Visitor
111 Views
Registered: ‎07-30-2019

Kintex 7 boards Fabrication detail ( especially KC705 ).

Hello Sir,

We have run our project on Kintex 7 evaluation board (  KC705 ) & got the resource utilization details like LUTs, BRAM, IOs, etc.

Now we are focusing on make ASIC of our project at 22 nm technology. From one of the document relation 7 Series we know, all 7 Series boards are fabricated at 28 nm technology. So, please help us to find out the detail of fabrication like How many NAND gates required to make 1 LUT. Size of RAMB18 & RAMB36.

Guide us from where & how we can get detail like mentioned above so that we can change that resource utilization into 22 nm technology.

Waiting for your prompt response.

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Scholar dpaul24
Scholar
107 Views
Registered: ‎08-07-2014

Re: Kintex 7 boards Fabrication detail ( especially KC705 ).

@vinayps,

So, please help us to find out the detail of fabrication like How many NAND gates required to make 1 LUT. Size of RAMB18 & RAMB36.

I am afriad you won't get such an answer. Xilinx confidential info!

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Visitor vinayps
Visitor
105 Views
Registered: ‎07-30-2019

Re: Kintex 7 boards Fabrication detail ( especially KC705 ).

Is there a way to know how much my design utilize the resource in term of gates & bit size.

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Scholar dpaul24
Scholar
89 Views
Registered: ‎08-07-2014

Re: Kintex 7 boards Fabrication detail ( especially KC705 ).

@vinayps,

It is a bit tricky. Read these...

https://forums.xilinx.com/t5/Other-FPGA-Architectures/equivalent-ASIC-gate-count/td-p/945868

https://forums.xilinx.com/t5/UltraScale-Architecture/Comparing-ASIC-gate-equivalent-with-XU-LUTs/m-p/893795?advanced=false&collapse_discussion=true&q=gate%20count&search_type=thread

 

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