07-31-2019 12:08 AM
We have run our project on Kintex 7 evaluation board ( KC705 ) & got the resource utilization details like LUTs, BRAM, IOs, etc.
Now we are focusing on make ASIC of our project at 22 nm technology. From one of the document relation 7 Series we know, all 7 Series boards are fabricated at 28 nm technology. So, please help us to find out the detail of fabrication like How many NAND gates required to make 1 LUT. Size of RAMB18 & RAMB36.
Guide us from where & how we can get detail like mentioned above so that we can change that resource utilization into 22 nm technology.
Waiting for your prompt response.
07-31-2019 12:10 AM
So, please help us to find out the detail of fabrication like How many NAND gates required to make 1 LUT. Size of RAMB18 & RAMB36.
I am afriad you won't get such an answer. Xilinx confidential info!
07-31-2019 12:13 AM
Is there a way to know how much my design utilize the resource in term of gates & bit size.
07-31-2019 12:22 AM
It is a bit tricky. Read these...