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Visitor
Visitor
7,071 Views
Registered: ‎09-07-2009

ML507 and VGA input with AD9980

Hi All,

 

I have an ML507 eval platform, and I am unsure about how to go about using the onboard AD9980 analog interface chip.

I know it has an IIC bus - and I can use this to access and program the registers, but how do I go about accesing the R G B data samples produced ?

Do I have to add a 'core' or 'IP' to be able to do this ? Is there anything available for this chip ? 

I have seen in XPS, in the PPC440 address map, devices like DDR, IIC_EEPROM, RS232 - I think I'm looking for  a way to add the AD9980 to this map?

 

Basically I want access to the sampled data.

 

Can anyone give me any hints or pointers on how I go about doing this, or if I am on the right track?

 

Thanks in advance

 

Matt

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Teacher
Teacher
7,061 Views
Registered: ‎07-09-2009

Had a quick look at the 507,

 

you seem out of luck for a pre configured application, which I must admit as a long standing Xilinx user is surprising, normaly they have good coverage of all the peripherals on the referance boards.

 

Anyway,

 

The Red, green and Blue , as well as sync signals are directly mapped onto pins of the FPGA.

 The data is sent to the FPGA with it's clock.

 

Your not trying to get the video data to the PPC are you ?

 

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Visitor
Visitor
7,056 Views
Registered: ‎09-07-2009

> The Red, green and Blue , as well as sync signals are directly mapped onto pins of the FPGA.

>  The data is sent to the FPGA with it's clock.

 

> Your not trying to get the video data to the PPC are you ?

 

Thanks for your response.

Please note - I am on a bit of a learning curve with VHDL.

 

I am trying to get the video data to the PPC - actually, it won't be video data, I would like to use the AD9980 as a high speed

A/D and process the samples from the PPC. But i'm not sure how complicated a job it will be to achieve this.

Ideally I would like to be able to plug in a module which allows access to samples in the PPC memory map.

I have read somewhere that there exists a TFT module for the Virtex-5 or ML507 which would allow something like this ?

 

So I think what I need is a module which

 - maps the FPGA "R G B" and clock signals

 - clocks in the samples to an area in RAM in the PPC memory map

 - asserts an interupt to the PPC when a certain number of samples have been taken

 

 

 

Am I on the right track ? and what sort of steps would I need to take to achieve this if I am ?

 

Thanks,

 

matt

 

 

 

 

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Xilinx Employee
Xilinx Employee
7,030 Views
Registered: ‎04-23-2008

See:

http://www.xilinx.com/support/documentation/ip_documentation/xps_tft.pdf

Note that only 640x480 resolution is supported, so this may or may not meet your needs.

 

-Brian

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